HCPL-1931 Avago Technologies US Inc., HCPL-1931 Datasheet - Page 7

• Manufacturer Part Number: HCPL-1931
• Description: Logic-Gate-Output Optocoupler,2-CHANNEL,1.5kV ISOLATION,DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-1931

• Voltage - Isolation: 1500VDC
• Number Of Channels: 2, Unidirectional
• Current - Output / Channel: 25mA
• Data Rate: 10Mbps
• Propagation Delay High - Low @ If: 60ns @ 13mA
• Current - Dc Forward (if): 60mA
• Input Type: AC, DC
• Output Type: Open Collector
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Typical Specifications
T
Notes:
10. CM
11. Measured between adjacent input leads shorted together, i.e. between 1, 2 and 4 shorted together and pins 5, 6 and 8 shorted together.
12. No external pull up is required for a high logic state on the enable input.
13. Measured between pins 1 and 2 or 5 and 6 shorted together, and pins 10 through 15 shorted together.
14. Parameters shall be tested as part of device initial characterization and after process changes. Parameters shall be guaranteed to the limits
15. Standard parts receive 100% testing at 25 C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25, 125, and -55 C (Subgroups 1
7
Parameter
Resistance (Input-Output)
Capacitance (Input-Output)
Input-Input Insulation
Leakage Current
Resistance (Input-Input)
Capacitance (Input-Input)
Propagation Delay Time of Enable
from V
Propagation Delay Time of Enable
from V
Output Rise Time (10-90%)
Output Fall Time (90-10%)
Input Capacitance
1. Bypassing of the power supply line is required, with a 0.1 F ceramic disc capacitor adjacent to each isolator. The power supply bus for the
2. Derate linearly at 1.2 mA/ C above T
3. Each channel.
4. Device considered a two terminal device: pins 1 through 8 are shorted together, and pins 9 through 16 are shorted together.
5. The t
6. The t
7. The t
8. The t
9. CM
A
= 25 C, V
isolators should be separate from the bus for any active loads, otherwise additional bypass capacitance may be needed to suppress regenerative
feedback via the power supply.
the output pulse.
the output pulse.
trailing edge of the output pulse.
leading edge of the output pulse.
V
V
specified for all lots not specifically tested.
and 9, 2 and 10, 3 and 11, respectively).
OUT
OUT
EH
EL
H
L
to V
to V
PLH
PHL
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state, i.e.
ELH
EHL
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state, i.e.
> 2.0 V.
< 0.8 V.
propagation delay is measured form the 6.5 mA point on the trailing edge of the input pulse to the 1.5 V point on the trailing edge of
propagation delay is measured from the 6.5 mA point on the leading edge of the input pulse to the 1.5 V point on the leading edge of
EH
enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V point on the
enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V point on the
EL
CC
= 5 V
A
= 100 C.
Symbol
R
C
t
t
C
R
I
ELH
EHL
C
t
t
I-O
I-O
I-I
I-I
I-I
r
f
I
Typ.
0.55
10
10
1.7
0.5
35
35
30
24
60
12
12
Units
nA
pF
pF
pF
ns
ns
ns
ns
Test Conditions
V
f = 1 MHz
V
V
f = 1 MHz
R
I
R
f = 1 MHz, V
I
I-O
I-I
I-I
L
L
= 13 mA, V
65% Relative Humidity,
= 510 , C
= 510 , C
= 500 Vdc, t = 5 s
= 500 Vdc
= 500 V dc
EH
I
L
L
= 0, PINS 1 to 2 or 5 to 6
= 15 pF,
= 15 pF, I
= 3 V, V
EL
I
= 0 V
= 13 mA
Fig.
6, 7
6, 7
Note
3, 13
3, 13
3, 7
3, 8
11
11
11
3
3
3