AD9269-40EBZ Analog Devices Inc, AD9269-40EBZ Datasheet - Page 11

• Manufacturer Part Number: AD9269-40EBZ
• Description: A/D Converter Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of AD9269-40EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9269
• Kit Contents: Software, Evaluation Board
• Number Of Adc's: 2
• Number Of Bits: 16
• Sampling Rate (per Second): 40M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 136.3mW @ 40MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9269
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
Pin No.
0, EP
1, 2
3
4 to 9, 11 to
18, 20, 21
10, 19, 28, 37
22
23
24
25 to 27, 29 to
36, 38 to 42
43
44
45
46
47
48
Mnemonic
AGND
CLK+, CLK−
SYNC
D0B (LSB) to
D15B (MSB)
DRVDD
ORB
DCOB
DCOA
D0A (LSB) to
D15A (MSB)
ORA
SDIO/DCS
SCLK/DFS
CSB
OEB
PDWN
Description
The exposed paddle is the only ground connection. It must be soldered to the PCB analog ground to
ensure proper functionality and heat dissipation, noise, and mechanical strength benefits.
Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.
Channel B Digital Outputs. D0B is the LSB; D15B is the MSB.
Digital Output Driver Supply (1.8 V to 3.3 V).
Channel B Out-of-Range Digital Output.
Channel B Data Clock Digital Output.
Channel A Data Clock Digital Output.
Channel A Digital Outputs. D0A is the LSB; D15A is the MSB.
Channel A Out-of-Range Digital Output.
SPI Data Input/Output (SDIO). Bidirectional SPI data I/O in SPI mode. 30 kΩ internal pull-down in SPI mode.
Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode. 30 kΩ internal
pull-up in non-SPI (DCS) mode.
SPI Clock (SCLK). Input in SPI mode. 30 kΩ internal pull-down.
Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal pull-down.
DFS high: twos complement output.
DFS low: offset binary output.
SPI Chip Select. Active low enable; 30 kΩ internal pull-up.
Digital Input. 30 kΩ internal pull-down.
Low: enable Channel A and Channel B digital outputs.
High: three-state outputs.
Digital Input. 30 kΩ internal pull-down.
High: power down device.
Low: run device, normal operation.
D0B (LSB)
NOTES
1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG GROUND
TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL
STRENGTH BENEFITS.
DRVDD
SYNC
CLK+
CLK–
D10B
D11B
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Figure 5. Pin Configuration
Rev. 0 | Page 11 of 40
(Not to Scale)
AD9269
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
ORA
D15A (MSB)
D14A
D13A
D12A
D11A
DRVDD
D10A
D9A
D8A
D7A
AD9269