AD9269-40EBZ Analog Devices Inc, AD9269-40EBZ Datasheet - Page 34

• Manufacturer Part Number: AD9269-40EBZ
• Description: A/D Converter Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of AD9269-40EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9269
• Kit Contents: Software, Evaluation Board
• Number Of Adc's: 2
• Number Of Bits: 16
• Sampling Rate (per Second): 40M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 136.3mW @ 40MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9269
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9269
Addr.
(Hex)
0x2A
0x2E
Digital feature control
0x100
0x101
0x110
0x111
0x112
0x113
0x114
0x116
0x117
0x118
0x119
0x11A
0x11B
0x11C
0x11D
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x100)
Bits[7:3]—Open
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Address 0x100, Bit 0) and the
clock divider sync enable bit (Address 0x100, Bit 1) are high,
Bit 2 allows the clock divider to sync to the first sync pulse it
receives and to ignore the rest. The clock divider sync enable bit
(Address 0x100, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 and Bit 0 are high, and the device is operating
in continuous sync mode as long as Bit 2 of the sync control is low.
Register
Name
Features
Output assign
Sync control
(global)
USR2
QEC Control 0
QEC Control 1
QEC gain
bandwidth control
QEC phase
bandwidth control
QEC DC
bandwidth control
QEC Initial Gain 0
QEC Initial Gain 1
QEC Initial Phase 0
QEC Initial Phase 1
QEC Initial DC I 0
QEC Initial DC I 1
QEC Initial DC Q 0
QEC Initial DC Q 1
(MSB)
Bit 7
Open
Open
Open
Enable
OEB
(Pin 47)
(local)
Open
Open
Open
Open
Open
Bit 6
Open
Open
Open
Open
Open
Open
Open
Open
Bit 5
Open
Open
Open
Freeze DC
Open
Initial phase, Bits[7:0]
Rev. 0 | Page 34 of 40
Initial DC Q, Bits[7:0]
Initial gain, Bits[7:0]
Initial DC I, Bits[7:0]
Open
Freeze
phase
Open
Bit 4
Open
Open
Initial gain, Bits[14:8]
Initial DC Q, Bits[13:8]
Initial DC I, Bits[13:8]
Open
Open
Open
Enable
GCLK
detect
Freeze
gain
Open
Bit 3
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions.
USR2 (Register 0x101)
Bit 7—Enable OEB (Pin 47)
Normally set high, this bit allows Pin 47 to function as the output
enable. If this bit is set low, it disables Pin 47.
Bits [6:4]—Open
Bit 3—Enable GCLK Detect
Normally set high, this bit enables a circuit that detects encode
rates below ~5 MSPS. When a low encode rate is detected, an
internal oscillator, GCLK, is enabled to ensure the proper operation
of several circuits. If this bit is set low, the detector is disabled.
Bit 2—Run GCLK
This bit enables the GCLK oscillator. For some applications
with encode rates below 10 MSPS, it may be preferable to set
this bit high to supersede the GCLK detector.
Initial phase, Bits[12:8]
KEXP_PHASE
KEXP_GAIN
Bit 2
Open
Open
Clock
divider
next
sync
only
Run
GCLK
DC
enable
Force
DC
KEXP_DC
Bit 1
Open
Open
Clock
divider
sync
enable
Open
Phase
enable
Force
phase
(LSB)
Bit 0
OR OE
(local)
0 =
ADC A
1 =
ADC B
(local)
Master
sync
enable
Disable
SDIO
pull-
down
Gain
enable
Force
gain
0x00
Default
Value
(Hex)
0x01
Ch A =
0x00
Ch B =
0x01
0x01
0x88
0x00
0x00
0x02
0x02
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Comments
Disable the OR pin
for the indexed
channel
Assign an ADC
to an output
channel
Enables internal
oscillator for
clock rates of
<5 MHz