AD9649-40EBZ Analog Devices Inc, AD9649-40EBZ Datasheet - Page 24

• Manufacturer Part Number: AD9649-40EBZ
• Description: 14-Bit, 40 MSPS, A/D Converter Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of AD9649-40EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9649
• Msl: MSL 3 - 168 Hours
• Mcu Supported Families: AD9649BCPZ-40
• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 40M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 61.6mW @ 40MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9649
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9649
SERIAL PORT INTERFACE (SPI)
The AD9649 SPI allows the user to configure the converter for
specific functions or operations through a structured register space
provided inside the ADC. The SPI gives the user added flexibility
and customization, depending on the application. Addresses are
accessed via the serial port and can be written to or read from via
the port. Memory is organized into bytes that can be further
divided into fields, which are documented in the Memory Map
section. For detailed operational information, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK (SCLK/DFS,
the SDIO (SDIO/PDWN), and the CSB (see Table 13). The SCLK
(a serial clock) is used to synchronize the read and write data
presented from and to the ADC. The SDIO (serial data input/
output) is a dual-purpose pin that allows data to be sent and
read from the internal ADC memory map registers. The CSB
(chip select bar) is an active-low control that enables or disables
the read and write cycles.
Table 13. Serial Port Interface Pins
Pin
SCLK
SDIO
CSB
SCLK
SDIO
CSB
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Function
Serial clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip select bar. An active-low control that gates the read
and write cycles.
t
S
R/W
t
DS
W1
W0
t
DH
A12
t
HIGH
A11
Figure 55. Serial Port Interface Timing Diagram
t
LOW
A10
A9
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t
CLK
A8
A7
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 55 and
Table 5.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in high impedance mode. This mode turns
on any SPI pin secondary functions.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits, as shown in Figure 55.
All data is composed of 8-bit words. The first bit of the first byte in
a multibyte serial data transfer frame indicates whether a read com-
mand or a write command is issued. This allows the serial data
input/output (SDIO) pin to change direction from an input to
an output at the appropriate point in the serial frame.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Data can be sent in MSB-first mode or in LSB-first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this
and other features, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI.
D5
D4
D3
D2
D1
D0
t
H
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