AD9649-40EBZ Analog Devices Inc, AD9649-40EBZ Datasheet - Page 28

• Manufacturer Part Number: AD9649-40EBZ
• Description: 14-Bit, 40 MSPS, A/D Converter Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of AD9649-40EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9649
• Msl: MSL 3 - 168 Hours
• Mcu Supported Families: AD9649BCPZ-40
• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 40M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 61.6mW @ 40MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9649
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9649
Addr.
(Hex)
0x14
0x15
0x16
0x17
0x19
0x1A
0x1B
0x1C
0x24
0x2A
Digital feature control register
0x101
Register Name
Output mode
Output adjust
Output phase
Output delay
USER_PATT1_LSB
USER_PATT1_MSB
USER_PATT2_LSB
USER_PATT2_MSB
BIST signature LSB
OR/MODE select
USR2
(MSB)
Bit 7
00 = 3.3 V CMOS
10 = 1.8 V CMOS
DCO
output
polarity
0 =
normal
1 = inv
Enable
DCO
delay
B7
B15
B7
B15
Open
1
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
3.3 V DCO
Bit 6
Open
Open
B6
B14
B6
B14
Open
Open
Bit 5
Open
Open
Enable
data
delay
B5
B13
B5
B13
Open
Open
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes
(default)
11 = 4 stripes
1.8 V DCO
BIST signature, Bits[7:0]
Bit 4
Output
disable
Open
B4
B12
B4
B12
Open
Open
Rev. 0 | Page 28 of 32
Open
B3
B11
B3
B11
Open
Enable
GCLK
detect
Bit 3
Open
Open
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
3.3 V data
Bit 2
Output
invert
B2
B10
B2
B10
Open
Run
GCLK
(Value is number of input clock
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Input clock phase adjust,
DCO/data delay, Bits[2:0]
cycles of phase delay)
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
Bit 1
00 = offset binary
01 = twos
complement
10 = gray code
11 = offset binary
B1
B9
B1
B9
Open
Open
Bits[2:0]
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes
(default)
11 = 4 stripes
1.8 V data
(LSB)
Bit 0
B0
B8
B0
B8
0 =
MODE
1 = OR
(default)
Disable
SDIO
pull-
down
Def.
Value
(Hex)
0x00
0x22
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x88
Default
Notes/
Comments
Configures the
outputs and the
format of the
data.
Determines
CMOS output
drive strength
properties.
On devices that
use global clock
divide, deter-
mines which
phase of the
divider output is
used to supply
the output clock;
internal latching
is unaffected.
Sets the fine
output delay of
the output clock
but does not
change internal
timing.
User-defined
Pattern 1 LSB.
User-defined
Pattern 1 MSB.
User-defined
Pattern 2 LSB.
User-defined
Pattern 2 MSB.
Least significant
byte of BIST sig-
nature, read only.
Selects I/O
functionality in
conjunction with
Address 0x08 for
MODE (input) or
OR (output) on
External Pin 23.
Enables internal
oscillator for
clock rates of
<5 MHz.