EVAL-AD7985EBZ Analog Devices Inc, EVAL-AD7985EBZ Datasheet - Page 21

• Manufacturer Part Number: EVAL-AD7985EBZ
• Description: 16-Bit A/D Converter Eval. Board
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7985EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD7985
• Kit Contents: Board
• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 2.5M
• Data Interface: SPI™, QSPI™, MICROWIRE™, and DSP
• Inputs Per Adc: 1 Differential
• Input Range: 0 ~ 5 V
• Power (typ) @ Conditions: 15.5mW @ 2.5MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7985
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7985 devices are
connected to an SPI-compatible digital host. A connection dia-
gram example using two AD7985 devices is shown in Figure 30,
and the corresponding timing is given in Figure 31.
With SDI high, a rising edge on CNV initiates a conversion,
selects CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase
and the subsequent data readback. (If SDI and CNV are low,
SDO is driven low.) Prior to the minimum conversion time,
SDI can be used to select other SPI devices, such as analog multi-
plexers, but SDI must be returned high before the minimum
t
SSDICNV
ACQUISITION
CNV
SCK
SDO
SDI
(n – 1)
t
HSDICNV
END DATA (n – 2)
CONVERSION (n – 1)
t
EN
t
DATA
14
2
t
CONV
15
1
SDI
16
0
Figure 31. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
Figure 30. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
AD7985
CNV
SCK
t
(I/O QUIET
HSDO
TIME)
t
EN
t
CYC
SDO
15
Rev. A | Page 21 of 28
1
SDI
14
ACQUISITION (n)
2
t
ACQ
BEGIN DATA (n – 1)
AD7985
13
CNV
SCK
conversion time elapses and then held high for the maximum
possible conversion time to avoid the generation of the busy
signal indicator.
When the conversion is complete, the AD7985 enters the
acquisition phase and powers down. Each ADC result can be
read by bringing its SDI input low, which consequently outputs
the MSB onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided that it has an acceptable hold time. After the 16
SCK falling edge, SDO returns to high impedance and another
AD7985 can be read.
t
t
HSDO
DSDO
SDO
(I/O QUIET
TIME)
CS2
CS1
CONVERT
DATA IN
CLK
DIGITAL HOST
t
QUIET
t
DIS
CONVERSION (n)
END DATA (n – 1)
14
t
2
DATA
t
CONV
15
1
t
SCK
16
0
t
(I/O QUIET
DIS
TIME)
AD7985
ACQUISITION
(n + 1)
th