HW-V5-ML505-UNI-G Xilinx Inc, HW-V5-ML505-UNI-G Datasheet - Page 13
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HW-V5-ML505-UNI-G
Manufacturer Part Number
HW-V5-ML505-UNI-G
Description
KIT, EVAL PLATFORM, VIRTEX-5 LXT, ML505
Manufacturer
Xilinx Inc
Datasheet
1.HW-V5-ML505-UNI-G.pdf
(31 pages)
Specifications of HW-V5-ML505-UNI-G
Kit Contents
RoHS Compliant
Svhc
No SVHC (15-Dec-2010)
Development Tool Type
Hardware / Software - Evaluation Kit
Silicon Manufacturer
Xilinx
Core Architecture
Virtex
Silicon Family Name
Virtex-5
Features
Linear Flash,
Rohs Compliant
Yes
ML505/ML506/ML507 Getting Started Tutorial
UG348 (v3.0.3) June 18, 2009
R
9.
10. Click OK → OK to accept the settings.
11. Connect the DVI monitor or the VGA monitor with DVI-to-VGA adapter to the board,
12. Turn on the ML50x board’s main power switch and press the SYSACE RESET button.
13. Extract the associated training lab files to your local computer.
For Character delay, enter 20.
if available.
After the FPGA has been programmed, the LEDs in the lower left corner should be:
♦
♦
♦
♦
♦
Note:
Unzip the training lab files to a working directory, name the directory, and make note
of the directory’s name. This directory with the extracted files is referred to as
<LAB_DIR> in this tutorial.
Bus Error 1 and 2 = off
FPGA INIT = green
FPGA DONE = green
System ACE “Err” = off
System ACE “Stat” = green
When the CF card is ejected or not installed, the System ACE “Err” LED blinks.
www.xilinx.com
Figure 5: ASCII Setup
UG348_05_040408
[Ref 3]
Board Setup
13