IP-SRAM/QDRII Altera, IP-SRAM/QDRII Datasheet

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... MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com QDRII SRAM Controller MegaCore Version: Document Date: 9.1 November 2009 ...

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... Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in- formation and before placing orders for products or services ii QDRII SRAM Controller MegaCore Function User Guide . UG-IPQDRII-8.1 MegaCore Version 9.1 Altera Corporation ...

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... Step 2: Constraints ............................................................................................................................ 2–7 Step 3: Set Up Simulation ................................................................................................................ 2–7 Step 4: Generate ................................................................................................................................ 2–8 Simulate the Example Design ............................................................................................................ 2–11 Simulate with IP Functional Simulation Models ....................................................................... 2–11 Simulating With the ModelSim Simulator ................................................................................. 2–11 Simulating With Other Simulators .............................................................................................. 2–12 Simulating in Third-Party Simulation Tools Using NativeLink ............................................. 2–17 Edit the PLL .......................................................................................................................................... 2–18 Compile the Example Design ............................................................................................................ 2– ...

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... Board & Controller ......................................................................................................................... 3–31 Project Settings ................................................................................................................................ 3–33 MegaCore Verification ........................................................................................................................ 3–34 Simulation Environment ............................................................................................................... 3–34 Hardware Testing ........................................................................................................................... 3–34 Additional Information Revision History ............................................................................................................................... Info–i How to Contact Altera ..................................................................................................................... Info–i Typographic Conventions .............................................................................................................. Info–ii iv QDRII SRAM Controller MegaCore Function User Guide MegaCore Version 9.1 Altera Corporation ...

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... Preliminary support means the MegaCore function meets all functional requirements, but may still be undergoing timing analysis for the device family; it may be used in production designs with caution. MegaCore Version 9.1 Function ® QDRII Description 9.1 November 2009 IP-SRAM/QDRII 00A4 6AF7 MegaCore IP Library ® II software MegaCore 1–1 ...

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... Operates at 300 MHz for QDRII and QDRII+ SRAM Automatic concatenation of consecutive reads and writes (narrow local bus width mode only) Easy-to-use IP Toolbench interface IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators Support for OpenCore Plus evaluation shows a system-level diagram including the example design MegaCore Version 9 ...

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... You can replace the QDRII SRAM controller encrypted control logic in the example design with your own custom logic, which allows you to use the Altera clear-text resynchronization and pipeline logic and datapath with your own control logic. OpenCore Plus Evaluation With Altera’ ...

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... QDRII SRAM 200 MHz/800 Mbps. through with the Quartus II software version 9.1. 1–4 QDRII SRAM Controller MegaCore Function User Guide Simulate the behavior of a megafunction (Altera MegaCore function or AMPP SM megafunction) within your system Verify the functionality of your design, as well as evaluate its size ...

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... Stratix GX Devices (EP1S10 to EP1S40 & EP1SGX10 to EP1SGX40 Devices) (1) Notes to (1) Table 1–6. QDRII SRAM Maximum Clock Frequency Supported in Stratix Devices (EP1S60 to EP1S80 Devices) Notes to (1) Altera Corporation November 2009 These numbers apply to both commercial and industrial devices. Frequency (MHz) DLL-Based Implementation 300 200 ...

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... QDRII SRAM Controller MegaCore Function User Guide shows typical sizes in combinational adaptive look-up tables Combinational Logic ALUTs Registers 360 598 369 633 390 708 459 880 MegaCore Version 9.1 Memory Blocks M4K M512 – – 2 – 4 – Altera Corporation November 2009 ...

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... Design Flow To evaluate the QDRII SRAM Controller using the OpenCore Plus feature, include these steps in your design flow: 1. The QDRII SRAM Controller is part of the MegaCore IP Library, which is distributed with the Quartus II software and downloadable from the Altera website, www.altera.com. f For system requirements and installation instructions, refer to Software Installation and Figure 2– ...

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... This walkthrough requires the following steps: 2–2 QDRII SRAM Controller MegaCore Function User Guide 1 IP Toolbench is a toolbar from which you quickly and easily view documentation, specify parameters, and generate all of the files necessary for integrating the parameterized MegaCore function into your design. ...

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... Altera Corporation November 2009 “Create a New Quartus II Project” on page 2–3 “Launch IP Toolbench” on page 2–4 “Step 1: Parameterize” on page 2–5 “Step 2: Constraints” on page 2–7 “Step 3: Set Up Simulation” on page 2–7 “Step 4: Generate” on page 2–8 Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run the Quartus II software ...

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... QDRII SRAM Controller Walkthrough You have finished creating your new Quartus II project. Launch IP Toolbench To launch IP Toolbench in the Quartus II software, follow these steps 2–4 QDRII SRAM Controller MegaCore Function User Guide 1 When you specify a directory that does not already exist, a message asks if the specified directory should be created. ...

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... MegaCore function output files <project path>\<variation name>. 1 The <variation name> must be a different name from the project name and the top-level design entity name. Click Next to launch IP Toolbench. Click Step 1: Parameterize in IP Toolbench. 3–29). Set the memory type: a. Choose the Memory device. ...

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... SRAM controller-specific constraints to the Quartus II project so that the Quartus II software automatically applies the constraints script when you compile the example design. SRAM controller variation is turned on, for IP Toolbench to automatically update the example design file. PLL and you do not want the wizard to regenerate the PLL when you regenerate the variation ...

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... Figure 2–2. System Naming Other Logic PLL 14. IP Toolbench uses a prefix (e.g., qdrii_) for the names of all memory 15. Click Finish. Step 2: Constraints To choose the constraints for your device, follow these steps Step 3: Set Up Simulation An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model produced by the Quartus II software ...

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... The Quartus II IP File (.qip file generated by the MegaWizard interface, and contains information about a generated IP core. You are prompted to add this .qip file to the current Quartus II project at the time of file generation. In most cases, the .qip file contains all of the necessary assignments and information required to process the core or system in the Quartus II compiler ...

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... Table 2–1 project directory. The names and types of files specified in the IP Toolbench report vary based on whether you created your design with VHDL or Verilog HDL Table 2–1. Generated Files (Part (1), Filename <variation name>.bsf <variation name>.html <variation name>.vhd <variation name>_bb.v < ...

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... Quartus II project top-level entity. (2) <variation name> is the name you give to the controller you create with the Megawizard. (3) IP Tooblench replaces the string qdrii_sram with qdriiplus_sram for QDRII+ SRAM controllers. 2. You have finished the walkthrough. Now, simulate the example design (refer to (refer to Example Design” ...

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... Simulate with IP Functional Simulation Models You can simulate the example design using the IP Toolbench-generated IP functional simulation models. IP Toolbench generates a VHDL or Verilog HDL testbench for your example design, which is in the testbench directory in your project directory. f For more information on the testbench, refer to ...

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... Simulating With Other Simulators The IP Toollbench-generated Tcl script is for the ModelSim simulator only. If you prefer to use a different simulation tool, follow these instructions. You can also use the generated script as a guide. You also need to download and compile an appropriate memory model. 1 VHDL IP Functional Simulations ...

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... Table 2–2. Files to Compile—VHDL IP Functional Simulation Models Library altera_mf <QUARTUS ROOTDIR>/eda/sim_lib/altera_mf_components.vhd <QUARTUS ROOTDIR>/eda/sim_lib/altera_mf.vhd lpm <QUARTUS ROOTDIR>/eda/sim_lib/220pack.vhd <QUARTUS ROOTDIR>/eda/sim_lib/220model.vhd sgate <QUARTUS ROOTDIR>/eda/sim_lib/sgate_pack.vhd <QUARTUS ROOTDIR>/eda/sim_lib/sgate.vhd <device name> <QUARTUS ROOTDIR>/eda/sim_lib/<device name>_atoms.vhd <QUARTUS ROOTDIR>/eda/sim_lib/<device name>_components.vhd auk_qdrii_lib < ...

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... Verilog HDL IP Functional Simulations For Verilog HDL simulations with IP functional simulation models, follow these steps 2–14 QDRII SRAM Controller MegaCore Function User Guide Set the Tcl variable gRTL_DELAYS to 1, which tells the testbench to ...

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... Table 2–4. Files to Compile—Verilog HDL IP Functional Simulation Models (Part Library altera_mf_ver <QUARTUS ROOTDIR>/eda/sim_lib/altera_mf.v lpm_ver <QUARTUS ROOTDIR>/eda/sim_lib/220model.v sgate_ver <QUARTUS ROOTDIR>/eda/sim_lib/sgate.v <device name>_ver <QUARTUS ROOTDIR>/eda/sim_lib/<device name>_atoms.v Altera Corporation November 2009 altera_mf_ver ● lpm_ver ● sgate_ver ● <device name>_ver ● ...

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... Simulate the Example Design Table 2–4. Files to Compile—Verilog HDL IP Functional Simulation Models (Part Library auk_qdrii_lib <project directory>/<variation name>_auk_qdrii_sram_clk_gen.v <project directory>/<variation name>_auk_qdrii_sram_addr_cmd_reg.v <project directory>/<variation name>_auk_qdrii_sram_cq_cqn_group.v <project directory>/<variation name>_auk_qdrii_sram_read_group.v <project directory>/<variation name>_auk_qdrii_sram_capture_group_wrapper.v <project directory>/<variation name>_auk_qdrii_sram_resynch_reg.v <project directory>/<variation name>_auk_qdrii_sram_write_group.v < ...

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... You can perform a simulation in a third-party simulation tool from within the Quartus II software, using NativeLink. f For more information on NativeLink, refer to the Simulating Altera IP Using NativeLink chapter in volume 3 of the Quartus II Handbook. To set up simulation in the Quartus II software using NativeLink, follow these steps: 1 ...

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... The IP Toolbench-generated example design includes up to two PLLs (system PLL and fedback clock PLL), which have an input to output clock ratio of 1:1 and a clock frequency that you entered in IP Toolbench. In addition, IP Toolbench correctly sets all the phase offsets of all the relevant clock outputs for your design. You can edit either PLLs’ input clock to make it conform to your system requirements ...

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... For more information on the altpll megafunction, refer to the Quartus II Help or click Documentation in the altpll MegaWizard Plug-In. Compile the Before the Quartus II software compiles the example design it runs the IP Toolbench-generated Tcl constraints script, auto_add_constraints.tcl. Example Design The auto_add_qdrii_constraints.tcl script calls the add_constraints_for_<variation name>.tcl script for each variation in your design. The add_constraints_for_< ...

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... If you have “?” characters in the Quartus II Assignment Editor, the Quartus II software cannot find the entity to which it is applying the constraints, probably because of a hierarchy mismatch. Either edit the constraints script, or enter the correct hierarchy path in the Hierarchy tab (refer to step page 2– ...

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... With Altera's free OpenCore Plus evaluation feature, you can evaluate the QDRII SRAM Controller MegaCore function before you obtain a license. OpenCore Plus evaluation allows you to generate an IP functional simulation model, and produce a time-limited programming file. f For more information on OpenCore Plus hardware evaluation using the QDRII SRAM Controller MegaCore function, refer to Evaluation” ...

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... Set Up Licensing 2–22 QDRII SRAM Controller MegaCore Function User Guide MegaCore Version 9.1 Altera Corporation November 2009 ...

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... QDRII SRAM read and write requests, with the correct timing and concatenating consecutive addresses where applicable. The resynchronization and pipeline logic provides the resynchronization system, the training block, and the optional pipeline logic. The datapath contains all the I/O and the clock generation. ...

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... On the Avalon interface, all the signals are independent. The write channel comprises an Avalon interface and a small pipeline to perform two-cycle bursts. A finite state machine (FSM) controls the signaling to the Avalon interface and deals with the data from Avalon interface ...

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... Optional Block Read Data Read FSM Pipeline Address & Command Pipeline The optional address and command pipeline pipelines all commands and addresses by a predefined number of cycles. Altera Corporation November 2009 shows the resynchronization and pipeline logic block Resynchronization & Pipeline Logic ...

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... Block Description Write Data Pipeline The write data pipeline pipelines the write data by a specified number of clock cycles.The number of pipelines is equal to the address and command pipelines, because the controller already aligns the data, address and command correctly, therefore the amount of delay going to the I/O is identical ...

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... The RAM size ensures there is minimal latency, but there is enough slack to compensate for the training pattern realignment. Datapath Figure 3–4 on page 3–6 Altera Corporation November 2009 shows the datapath block diagram. MegaCore Version 9.1 QDRII SRAM Controller MegaCore Function User Guide Functional Description 3–5 ...

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... Block Description Figure 3–4. Datapath Block Diagram From Control Logic To Resynchronization 3–6 QDRII SRAM Controller MegaCore Function User Guide Address & Command Output Registers Address & Command Output Registers From Write FSM Capture Registers Capture Registers MegaCore Version 9.1 Datapath Clock Generator Address & ...

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... When captured, the controller synchronizes the two words on a double width bus. Altera Corporation November 2009 Address Read Write Write byte enable CQ/CQN group module Read capture registers MegaCore Version 9.1 QDRII SRAM Controller MegaCore Function User Guide Functional Description 3–7 ...

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... Block Description With more than one device, one cq/cqn pair and q bus are connected per device in the width direction. For a device depth of two, it shares the q and cq/cqn signals. All the signals go out of the block with their associated internal cq clock, so you can use Altera's resynchronization scheme or implement your own ...

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... The output of latch B is either real B or expected B, depending on the relationship between cq and cqn. To cover both cases, the usable part of B signal should be captured before going to the resynchronization FIFO buffers. Routing delay aligns the data with the clock. ...

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... If tethered mode is supported by all megafunctions in a design, the device can operate for a longer time or indefinitely For MegaCore functions, the untethered time out is 1 hour; the tethered time out value is indefinite. Megafunctions. “Interface Description” on page 3–10 “Signals” on page 3–22 MegaCore Version 9 ...

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... Non-consecutive addresses are split 3–14). shows an isolated write transaction on a burst of four (narrow 00010002 00010002 0001 0001 MegaCore Version 9.1 QDRII SRAM Controller MegaCore Function User Guide Functional Description Avalon “Bursts with 0001 0002 0002 0001 0001 ...

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... QDRII SRAM Controller MegaCore Function User Guide shows a burst of two, the controller takes the data straight 0001 0001 shows a burst of four (wide mode), all the data is MegaCore Version 9.1 0001 0002 0002 0001 0001 00 00 Altera Corporation November 2009 ...

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... Altera Corporation November 2009 01020304 01020304 0001 0001 shows the burst of four (narrow mode). When MegaCore Version 9.1 QDRII SRAM Controller MegaCore Function User Guide Functional Description 0001 0001 00 00 3–13 ...

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... A one-cycle write to address <a> followed straight away by a two- cycle transfer to addresses <b> and <b + 1> The second half of the transfer to <b> is paused for a clock cycle MegaCore Version 9.1 0001 0002 0003 0004 0004 0002 00 00 Figure 3–7 on page 3–11. Altera Corporation November 2009 ...

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... Read” on page 3–15 “Burst” on page 3–17 “Bursts with Pauses” on page 3–18 shows a read request from the Avalon read MegaCore Version 9.1 QDRII SRAM Controller MegaCore Function User Guide Functional Description 0001 0002 1103 1104 1105 1106 1106 1122 00 ...

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... Figure 3–13 burst of two. The principle is identical to the burst of four, but all the data bits coming back are transferred onto the Avalon interface. The timing on the QDRII SRAM interface is slightly different as the address is only present for half a clock cycle. ...

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... For the other two modes, there is no such concept as all the MegaCore Version 9.1 QDRII SRAM Controller MegaCore Function User Guide Functional Description 01020304 01020304 Figure 3–15 on 3–17 ...

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... The following two reads still get concatenated to make a burst of four, avoiding loss of bandwidth. 3–18 QDRII SRAM Controller MegaCore Function User Guide 0003 0002 Figure 3–16 on page 3–19 MegaCore Version 9.1 0102 0304 0304 04 shows a read Altera Corporation November 2009 ...

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... Four (Narrow Mode)” on page 3–19 “Burst of Two” on page 3–20 “Burst of Four (Wide Mode)” on page 3–21 Figure 3–17 on page MegaCore Version 9.1 QDRII SRAM Controller MegaCore Function User Guide Functional Description 0102 3132 3334 3334 34 3–20. 3–19 ...

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... QDRII SRAM Controller MegaCore Function User Guide 1002 1003 1718 3000 1000 3002 1002 Figure 3–18 on page 3–21 shows concurrent reads and writes in a MegaCore Version 9.1 0102 0304 0506 0708 18 08 Altera Corporation November 2009 0708 ...

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... Avalon interfaces. The first read is buffered and then the consecutive read is delayed by one clock cycle, refer to Altera Corporation November 2009 Figure 3–19 on page MegaCore Version 9.1 QDRII SRAM Controller MegaCore Function User Guide Functional Description 0102 0304 0304 04 3–22. 3–21 ...

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... Input Input Input MegaCore Version 9.1 9abc dfe0 dfe0 Description System clock derived from the PLL. Write clock derived from the PLL. Reset signal, which you can assert asynchronously, but you must deassert synchronously to avl_clk Delay bus for DLL to shift DQS inputs. ...

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... Input Avalon read address. Input Byte enable (active low). Input Device select for the read port. Input Avalon read request. Output Avalon read data to master. MegaCore Version 9.1 QDRII SRAM Controller MegaCore Function User Guide Functional Description Description Description Description 3–23 ...

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... Output shows the datapath interface signals. Direction Input Clock. Input Read address from the pipeline and resynchronization logic. Input Write address from the pipeline and resynchronization logic. Input Byte enable from the pipeline and resynchronization logic. Input Read from the pipeline and resynchronization logic. ...

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... Write signal from the pipeline and resynchronization logic. Input DLL delay control from the top-level design to shift the nominal 90 degrees. Output Capture clocks (CQ into soft logic) to the pipeline and resynchronization logic. Output Captured data—data after the IO to pipeline and resynchronization logic. ...

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... IP Toolbench generates the example PLLs with an input to output clock ratio of 1:1 and a clock frequency you entered in IP Toolbench. In addition IP Toolbench sets the correct phase outputs on the PLLs’ clocks. You can edit the PLLs to meet your requirements with the altpll MegaWizard Plug-In ...

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... Non-DQS mode only. Example Design IP Toolbench creates an example design that shows you how to instantiate and connect up the QDRII SRAM controller. The example design is a working system that can be compiled and used for both static timing checks and board tests. It also instantiates an example PLL and shows you how to generate the external clocks for the QDRII SRAM device ...

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... Megawizard. MegaCore Version 9.1 QDRII SRAM Model DLL Description Testbench for the example design. Example design. Example PLL, which you should configure to match your frequency. Example driver. QDRII SRAM controller. ...

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... Altera recommends that you replace the model with the specific model from your memory vendor. f For more details on how to run the simulation script, refer to the Example Design” on page Constraints IP Toolbench generates a constraints script, add_constraints_for_< ...

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... For QDRII, 1.5; for QDRII+, 2.0 or 2.5 Table 3–8: IP Toolbench allows you to enter up to 600 MHz, but Altera only supports the QDRII SRAM controller up to 300 MHz. MegaCore Version 9.1 Description A part number for a particular memory device. Choosing an entry other than Custom sets many of the parameters in the wizard to the correct value for the specified part ...

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... These registers help to achieve the required performance at higher frequencies. You can choose pipeline registers between the memory controller and the read data input. These registers help to achieve the required performance at higher frequencies. MegaCore Version 9.1 ...

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... Enter the pin loading to match your board and memory devices. Enter the pin loading to match your board and memory devices. Enter the pin loading to match your board and memory devices. MegaCore Version 9.1 Description Turn on if you want to choose the latency clock cycle. Choose the latency clock cycle. For example, if the default is 13, you can choose any value from ...

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... Parameter Automatically apply QDR When this option is turned on, the next time you compile, the Quartus II software SRAM controller-specific automatically runs the add constraints script. Turn off this option if you do not want constraints to the the script to run automatically. Quartus II project Update the example ...

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... Verification Simulation Environment Altera has carried out extensive tests using industry-standard models to ensure the functionality of the QDRII SRAM controller. In addition, Altera has carried out a wide variety of gate-level tests of the QDRII SRAM controller to verify the post-compilation functionality of the controller. Hardware Testing Table 3–18 hardware tested the QDRII SRAM controller. Table 3– ...

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... Updated the device support. ● Corrected burst of two timing diagram. ● Added information for new reset block in example design. ● Added new training signals and updated training group module description. ● Added extra resynchronization and pipeline logic information. ● Updated description of March 2007 7 ...

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... Indicates directory names, project names, disk drive names, file names, file name extensions, and software utility names. For example, \qdesigns directory, d: drive, and chiptrip.gdf file. Italic Type with Initial Capital Indicates document titles. For example, AN 519: Stratix IV Design Guidelines. ...