IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 5

• Manufacturer Part Number: IPR-PCI/MT64
• Description: IP CORE Renewal Of IP-PCI/MT64
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT64

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 64 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Revision History
Altera Corporation
Version
Table 2. PCI Compiler Revision History
4.1.1
4.1.0
April 2006
October 2005
Date
Table 2
●
●
●
●
●
●
●
●
●
●
Maintenance release; updated documentation and screen shots to reflect
release version.
Fixed the default installation path in the documentation.
Removed installation instructions from the PCI Compiler User Guide.
Moved the reference design and timing information from the release notes to
the user guide.
Added preliminary support for Stratix II GX and HardCopy II device families.
Updated support for Stratix II, MAX II, and Cyclone II device families.
Reduced device utilization for PCI-Avalon Bridge
Fixed the following MegaWizard Plug-In Manager flow problems:
- The CIS pointer default value was made to be 0x00000000 instead of
0x00000001
Fixed the following SOPC Builder flow problems:
-The prefetchable write transactions were made to disconnect at BAR
boundary.
- Fixed a configuration address translation bug that prevented the selection of
i
- Fixed the issue in which for 32-bit master read transactions, byte enables
from the Avalon side were not being passed to the PCI side.
- Corrected the issue where
register module is not implemented.
Fixed the following issues that affect both flows:
- The pci_mt64 did not end the PCI master transactions immediately following
the
bit write request and the PCI Target is asserting random wait states.
- In the case of an Address parity error detected by the PCI core, the PCI core
used to also enable the perrn drivers although it does not assert
- Fixed protocol violation where
transaction in the case of wait states on
- Fixed protocol violation where
after detecting
bit target with target wait states.
- Fixed a protocol violation where
single cycle DAC memory read transaction.
dsel=AD[31]
lm_lastn
shows the revision history for the PCI Compiler version 4.1.1.
stopn
assertion in the case of a 32-bit PCI target response to a 64-
asserted during 64-bit master write transaction to 32-
intan
Revision
stopn
framen
framen
was asserted after
irdyn
was asserted after the end of the
was not deasserted immediately
was asserted for one cycle during
.
reset
Revision History
if the Control
devseln
Preliminary
.
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