IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 8

• Manufacturer Part Number: IPR-PCI/MT64
• Description: IP CORE Renewal Of IP-PCI/MT64
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT64

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 64 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Compiler
8
Preliminary
Version
Table 2. PCI Compiler Revision History
2.0.0
August 2001
Date
●
Added PCI MegaCore function features:
●
●
●
●
●
●
Improved the look and feel of the PCI Compiler wizard and added support for
new PCI MegaCore features. Updated the PCI MegaCore functions to v2.0.0.
See the revision history in the readme files for each individual PCI MegaCore
function for details on the changes. Included behavioral simulation models for
all PCI MegaCore functions to support VHDL and Verilog HDL simulators.
Included an open source PCI testbench in VHDL and Verilog HDL. Updated
pci_mt32 and pci_mt64 reference designs for pci_mt64 and pci_mt32
MegaCore functions v2.0.0. Due to enhanced support in the PCI Compiler
wizard for constraint files, the command line utility set_constraint was
removed from the PCI Compiler. Use the PCI Compiler MegaWizard to create
project specific constraint files for your design.
Added the Add Internal Data Steering Logic for 32/64-Bit Systems option,
which provides improved logic optimization to let you attain 66 MHz
performance more easily. When disabled, this option removes the internal
data steering logic from
valid data on
transaction. When enabled, valid data is available on
l_beno[7..0]
compatible with previous versions of pci_mt64. The Add Internal Data
Steering Logic for 32/64-Bit Systems option is available in the PCI Compiler
wizard; the option sets bit 14 of the
Added the Host Bridge Enable option to allow the pci_mt64 function to be
used as a system host. When enabled, the option causes the pci_mt64
MegaCore function to power up with the master enable bit in the command
register hardwired to 1 and allows the master interface to initiate configuration
read and write transactions to the internal configuration space. The Host
Bridge Enable option is available in the PCI Compiler wizard; the option sets
bit 13 of the
Added the 64-Bit Only Devices option to provide enhanced functionality for
64-bit only systems. When enabled, the option improves the latency of the
pci_mt64 master PCI signals (especially
32-bit transactions. This feature also enables single-cycle master writes and
adds the functionality previously offered through the
parameter. The 64-Bit Only Devices option is available in the PCI Compiler
wizard; the option sets bit 16 of the
The PCI_64BIT_SYSTEM parameter has been disabled. You must enable
this option in designs that previously used the
parameter.
Added the ability to permanently disable the pci_mt64 master latency timer
registerm which prevents the latency timer from expiring. The option is
available in the PCI Compiler wizard; the option sets bit 15 of the
ENABLE_BITS
Enabled the master to keep the PCI bus when
latency timer expires. Additionally, the local side signal
indicates that the latency timer has expired, is not set until
ENABLE_BITS
l_dato[31..0]
parameter.
during a 32-bit transaction and the operation is fully
l_dato[63..32]
parameter.
Revision
and
ENABLE_BITS
ENABLE_BITS
l_beno[3..0]
irdyn
and
PCI_64BIT_SYSTEM
) to be the same as those in
gntn
l_beno[7..4]
parameter.
l_dato[63..0]
PCI_64BIT_SYSTEM
parameter.
is asserted and the
lm_tsr[4],
during a 32-bit
Altera Corporation
gnt
is removed.
, providing
which
and