IPR-PCI/T32 Altera, IPR-PCI/T32 Datasheet - Page 155

• Manufacturer Part Number: IPR-PCI/T32
• Description: IP CORE Renewal Of IP-PCI/T32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/T32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 3–25. Disconnect in a Burst Write Transaction
Note to
(1)
Altera Corporation
January 2011
(1) l_dato[63..32]
(1) l_hdat_ackn
(1) l_beno[7..4]
(1) l_ldat_ackn
(1) ad[63..32]
This signal is not applicable to either the pci_mt32 or pci_t32 MegaCore functions.
(1) cben[7..4]
l_adro[31..0]
l_dato[31..0]
l_cmdo[3..0]
l_beno[3..0]
lt_tsr[11..0]
(1) ack64n
(1) req64n
cben[3..0]
lt_framen
(1) par64
ad[31..0]
devseln
lt_discn
lt_dxfrn
Figure
lt_ackn
framen
lt_rdyn
stopn
irdyn
trdyn
par
clk
1
3–25:
2
000
Adr
7
3
Figure 3–25
transaction where multiple data phases are completed.
applies to all PCI MegaCore functions, excluding the 64-bit extension
signals as noted for pci_mt32 and pci_t32. One additional data phase
will be completed on the local side following the assertion of lt_discn.
Adr-PAR
4
BE0_H
PCI Compiler Version 10.1
BE0_L
D0_H
D0_L
5
shows an example of a disconnect during a burst target write
381
D0-H-PAR
D0-L-PAR
6
7
BE0_H
BE0_L
BE1_H
BE1_L
D1_H
D0_H
D1_L
D0_L
8
Adr
7
D1-H-PAR
D1-L-PAR
BE2_H
BE1_H
BE2_L
BE1_L
D2_L
D2_H
D1_L
D1_H
781
9
D2-H-PAR
D2-L-PAR
BE2_H
BE2_L
D2_L
D2_H
BE3_H
D3_L
D3_H
BE3_L
10
D3-L-PAR
D3-H-PAR
11
381
Functional Description
Figure 3–25
12
13
000
3–81
14