IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet

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... Altera Transceiver PHY IP Core User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01080-1.11 Altera Transceiver PHY IP Core Document last updated for Altera Complete Design Suite version: Document publication date: User Guide 10.1 December 2010 Subscribe ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... Clocks, Reset, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13 PMA Channel Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14 PMA Control and Status Interface Signals–Soft IP Implementation (Optional 4–14 PMA Control and Status Interface Signals–Hard IP Implementation (Optional 4–15 TimeQuest Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16 December 2010 Altera Corporation Contents Altera Transceiver PHY IP Core User Guide ...

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... Transceiver Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14 Optional Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14 Dynamic Partial Reconfiguration I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15 Chapter 8. Low Latency PHY IP Core Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2 Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2 Parameter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5 Altera Transceiver PHY IP Core User Guide Contents December 2010 Altera Corporation ...

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... PCI Express PHY (PIPE 10–4 Parameter Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–4 Port Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–5 Custom PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–8 Parameter Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–8 Port Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–9 Additional Information Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–3 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–3 December 2010 Altera Corporation v Altera Transceiver PHY IP Core User Guide ...

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... Altera Transceiver PHY IP Core User Guide Contents December 2010 Altera Corporation ...

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... Custom PHY Low latency PHY December 2010 Altera Corporation Avalon Interface Specifications. Table 1–1 indicates. Soft PCS Hard PCS No Yes Yes No Yes No Yes No Yes No Yes Altera Transceiver PHY IP Core User Guide 1. Introduction ® ® V Hard PMA Yes No Yes Yes Yes Yes Yes ...

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... Tx and Rx To MAC Avalon-MM To Control & Status Embedded Controller Hard logic for Stratix V, variable for Stratix IV Soft logic for Stratix IV and Stratix V Altera Transceiver PHY IP Core User Guide PCS Customized functionality Rx Deserializer as required for: 10GBase-R XAUI Tx Serializer Interlaken PCI Express PIPE ...

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... TX PLL to create the parallel clock inputs the TX channel PMA and PCS modules. The parallel clocks for each channel are carefully tuned to keep the clock skew below 150 ps. Figure 1–2 December 2010 Altera Corporation ). It converts parallel input data streams to serial OD illustrates bonded mode for Stratix V devices. 1–3 Altera Transceiver PHY IP Core User Guide ...

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... Figure 1–2. Stratix V Device Bonded Mode Clocking Reference clock input pin Tx data Rx data Tx data Rx data Altera Transceiver PHY IP Core User Guide Channel PLL High Low speed frequency parallel Clock Gen clock clock(s) Buffer Tx PLL (CGB) /n, /m Transceiver PMA PCS Ser ...

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... PMA PCS PMA Ser CDR DeSer Data Clock Ser = Serializer DeSer = DeSerializer illustrates mode for Stratix V devices. FPGA-fabric interface Low speed parallel clock(s) PCS Tx PCS Rx PCS Low speed parallel clock(s) PCS Tx PCS Rx PCS Altera Transceiver PHY IP Core User Guide 1–5 ...

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... After the PLL locks, tx_ready is asserted. 2. After offset cancellation completes rx_oc_busy is deasserted. (Offset cancellation corrects for process variations which may result in analog voltages that are offset from the required ranges.) Altera Transceiver PHY IP Core User Guide II software automatically selects the power-down channel feature, Bonded — ...

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... PCS and PMA Control and Status Register Memory Map S Dynamic Reconfiguration S in volume 4 of the Stratix IV Device Handbook for Reset Control and Power Down 1–7 pll_powerdown phy_mgmt_clk_reset tx_ready to / from user logic rx_ready in volume 2 of the Stratix V Device Altera Transceiver PHY IP Core User Guide ...

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... Figure 1–6. Serial Loopback FPGA Fabric To FPGA fabric for verification Unsupported Features The protocol-specific PHYs are not supported in SOPC Builder in the current release. Altera Transceiver PHY IP Core User Guide 1–2.) PCI Express Base Specification. Figure 1–6 Transceiver Tx PMA Tx PCS Serializer Rx PMA ...

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... This chapter provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera IP core. The Altera IP Library is installed as part of the Quartus II installation process. You can select and parameterize any Altera IP core from the library. Altera provides an integrated parameter editor that allows you to customize IP cores to support a wide variety of applications ...

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... Create a Quartus II project using the New Project Wizard available from the File menu the Quartus II software, launch the MegaWizard Plug-in Manager from the Tools menu, and follow the prompts in the MegaWizard Plug-In Manager interface to create or edit a custom IP core variation. Altera Transceiver PHY IP Core User Guide Select Design Flow Qsys or SOPC Builder Flow ...

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... Chapter 2: Getting Started MegaWizard Plug-In Manager Flow 3. To select a specific Altera IP core, click the IP core in the Installed Plug-Ins list in the MegaWizard Plug-In Manager. 4. Specify the parameters on the Parameter Settings pages. For detailed explanations of these parameters, refer to the “Parameter Settings” chapter in this document. ...

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... For a complete list of models or libraries required to simulate your IP core, refer to the scripts provided with the testbench. For more information about simulating Altera IP cores, refer to Designs in volume 3 of the Quartus II Handbook. Altera Transceiver PHY IP Core User Guide ...

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... The Altera 10GBASE-R PHY IP core implements the functionality described in 802.3 Clause 49. It delivers serialized data to an optical module that drives multi-mode optical fiber at a line rate of 10.3125 Gbps multi-channel implementation of 10GBASE-R, each channel of the 10GBASE-R PHY IP core operates independently. You can instantiate multiple channels to achieve higher bandwidths. The PCS is available in soft logic for Stratix IV GT devices ...

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... For more detailed information about the 10GBASE-R transceiver channel datapath, clocking, and channel placement, refer to the “10GBASE-R” section in the Protocol Configurations in Stratix V Devices Altera Transceiver PHY IP Core User Guide Figure 3–1 illustrates, the Avalon-MM bridge Avalon-MM Hard PCS Hard PMA ...

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... DC and Switching Characteristics Stratix IV devices or of the Stratix V Handbook for Stratix V devices. December 2010 Altera Corporation Item IP-10GBASERPCS (primary) (Note 1) IPR-10GBASERPCS (renewal) Device Family Final Preliminary No support chapter in volume 3 of the Stratix IV Handbook for DC and Switching Characteristics for Stratix V Devices 3–3 Description 10 ...

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... Use external PMA control and On/Off reconfig Starting channel number 0–96 f For a description of the Analog options, refer the to page 8–4. Altera Transceiver PHY IP Core User Guide Logic Registers (Bits) 5200 4100 15600 1300 38100 32100 Table 3–4 lists the settings available on General Options tab. ...

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... SOPC Builder User Guide. 10GBASE-R Top-Level Signals rx_serial_data <n> tx_serial_data <n> gxb_pdn pll_locked pll_pdn cal_blk_pdn rx_oc_busy cal_blk_clk reconfig_to_gxb[3:0] reconfig_from_gxb[16:0] rx_block_lock rx_hi_ber pll_ref_clk 3–5 Transceiver Serial Data Signals for External PMA and Reconfiguration Stratix IV only Status Clock f Altera Transceiver PHY IP Core User Guide ...

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... Altera Transceiver PHY IP Core User Guide Description Contains 8 lanes of data and control for XGMII. Each lane consists of 8 bits of data and 1 bit of control. Lane 0–[7:0]/[8] ■ Lane 1–[16:9]/[17] ■ Lane 2–[25:18]/[26] ■ ...

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... FIFO between the MAC and SDR XGMII RX interface. XGMII Signal Name xgmii_sdr_data[7:0] xgmii_sdr_ctrl[0] xgmii_sdr_data[15:8] 3–7 Description Lane 5 control Lane 6 data Lane 6 control Lane 7 data Lane 7 control Description Lane 0 data Lane 0 control Lane 1 data Altera Transceiver PHY IP Core User Guide ...

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... Refer to the “Typical Slave Read and Write Transfers” and “Master Transfers” sections in the “Avalon Memory-Mapped Interfaces” chapter of the timing diagrams. Altera Transceiver PHY IP Core User Guide XGMII Signal Name xgmii_sdr_ctrl[1] xgmii_sdr_data[23:16] xgmii_sdr_ctrl[2] xgmii_sdr_data[31:24] xgmii_sdr_ctrl[3] xgmii_sdr_data[39:32] ...

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... You must write clear the reset condition. Writing a 1 causes the RX digital reset signal to be asserted, resetting the RX digital channels enabled in reset_ch_bitmask. You must write clear the reset condition. 3–9 Description 1–2, performs a standard Altera Transceiver PHY IP Core User Guide ...

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... R RX_SYNC_HEAD_ERROR [6] R RX_SCRAMBLER_ERROR Altera Transceiver PHY IP Core User Guide Name PMA Channel Control and Status Writing channel <n> puts channel <n> in serial loopback mode. When asserted, the signal level circuit senses if the specified voltage level exists at the receiver input buffer. Bit < ...

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... Stratix V devices. From Block: Block synchronizer Description Asserted to indicate that the block synchronizer has established synchronization. Asserted by the BER monitor block to indicate a high bit error rate. chapter in volume 2 of the Stratix IV Device 3–11 Description Altera Transceiver PHY IP Core User Guide ...

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... MHz clock. illustrates the clock generation and distribution for Stratix IV devices. Figure 3–4. Stratix IV GT Clock Generation and Distribution 10GBASE-R Transceiver Channel - Stratix xgmii_tx_clk RX 64 xgmii_rx_clk 156.25 MHz Altera Transceiver PHY IP Core User Guide PCS TX PCS (soft IP) (hard IP) /2 257.8125 516.625 MHz ...

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... December 2010 Altera Corporation 40 TX PCS TX PMA TX PLL 257.8125 MHz 40 RX PCS RX PMA 257.8125 MHz GPLL 8/33 Description TX PLL reference clock which must be 644.53725 MHz. 3–13 10.3125 Gbps serial pll_ref_clk 644.53125 MHz 10.3125 Gbps serial Altera Transceiver PHY IP Core User Guide ...

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... You can also apply LogicLock to the alt_10gbaser_pcs and slightly expand the lock region to meet timing. h For more information about LogicLock, refer to Help. Altera Transceiver PHY IP Core User Guide (Note 1) Receiver input data Transmitter output data Input When asserted, powers down the entire GX block. Active high. ...

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... December 2010 Altera Corporation provides the Synopsys Design Constraints File (.sdc) timing constraints -period 20.00 -waveform { 0.000 10.000 } [get_ports 3–15 } [get_ports Altera Transceiver PHY IP Core User Guide ...

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... Set Input Transition #************************************************************** 1 This .sdc file is only applicable to the 10GBASE-R PHY IP core when compiled in isolation. You can use reference to help in creating your own .sdc file. Altera Transceiver PHY IP Core User Guide Chapter 3: 10GBASE-R PHY IP Core TimeQuest Timing Constraints December 2010 Altera Corporation ...

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... IEEE 802.3 Clause 48 XAUI IP Core PCS 8B/10B Word Aligner Phase Comp chapter of the Stratix V Device Handbook. Item IP-XAUIPCI (primary)–soft PCS (Note 1) IPR-XAUIPCS (renewal)–soft PCS 4. XAUI PHY IP Core specification to 4 Hard PMA 3.125 Gbps serial Transceiver Description 10.1 December 2010 ...

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... Preliminary support—Verified with preliminary timing models for this device. Table 4–2 shows the level of support offered by the XAUI IP core for Altera device families. Table 4–2. Device Family Support Arria II GX–hard PCS and hard PMA Cyclone IV GX–hard PCS and hard PMA Stratix IV GX and GT devices– ...

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... General Options tab. Value The target device family. The physical starting channel number in the Altera device for channel 0 of this XAUI PHY. In Arria II GX, Cyclone IVGX, and Stratix IV devices, this starting channel number must multiple of 4. There are no numbering restrictions for Stratix V devices. ...

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... Figure 4–2. XAUI PHY Using One Channel Low Latency PHY Controller Hard XAUI PHY SDR XGMII 72 bits @ 156.25 Mbps To MAC System Interconnect Fabric For more information about transceiver reconfiguration, refer to Transceiver Reconfiguration Altera Transceiver PHY IP Core User Guide Transceiver Quad 0 Inter- PCS Alt_PMA leave S PMA Channel S Avalon-MM ...

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... Reset December 2010 Altera Corporation SOPC Builder User Guide. xaui_rx_serial_data[3:0] xaui_tx_serial_data[3:0] rx_channelaligned rx_disperr[7:0] rx_errdetect[7:0] rx_syncstatus[7:0] cal_blk_powerdown gxb_powerdown pll_powerdown pll_locked reconfig_fromgxb[67:0] reconfig_togxb[3:0] rx_ready tx_ready Altera Transceiver PHY IP Core User Guide 4–5 Figure 4–4 Transceiver Serial Data Rx Status Optional Optional PMA Channel Controller ...

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... For more information about the Avalon-ST protocol, including timing diagrams, refer to the Avalon Interface Altera Transceiver PHY IP Core User Guide xaui_rx_serial_data[3:0] xaui_tx_serial_data[3:0] rx_invpolarity[3:0] rx_set_locktodata[3:0] rx_is_lockedtodata[3:0] rx_set_locktoref[3:0] rx_is_lockedtoref[3” ...

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... Sink Lane 1–[25:18]/[26], [34:27]/[35] ■ Lane 2–[43:36]/[44], [52:45]/[53] ■ Lane 3–[61:54]/[62],[70:63]/[71] ■ Output The XGMII SDR RX MAC interface clock which runs at 156.25 MHz. 4–7 [15:8] [7:0] [39:32] [7:0] Description Description Altera Transceiver PHY IP Core User Guide ...

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... R pma_tx_pll_is_locked 0x041 [31:0] RW reset_ch_bitmask Altera Transceiver PHY IP Core User Guide describes the signals that comprise the Avalon-MM PHY Direction Input Avalon-MM clock input. Global reset signal that resets the entire XAUI PHY. A positive edge Input on this signal triggers the reset controller. ...

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... RX data, and that the RX CDR has changed from LTR to LTD mode. Bit <n> corresponds to channel <n>. When asserted, indicates that the RX CDR PLL is locked to the reference clock. Bit <n> corresponds to channel <n>. 4–9 Description 1–2, performs a standard Altera Transceiver PHY IP Core User Guide ...

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... Reserved [15:8] disperr[7:0] 0x085 R [7:0] errdetect[7:0] Altera Transceiver PHY IP Core User Guide Register Name XAUI PCS Resets the TX PCS clock domain. To block: RX PCS. Resets the RX PCS clock domain. To block: TX PCS. Inverts the polarity of corresponding bit on the RX interface. Bit 0 maps to lane 0 and so on. ...

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... Reading the value of the phase_comp_fifo_error register clears the bits. From block: TX phase compensation FIFO. Setting this bit to 1 shortens the duration of reset and loss timer when simulating. Altera recommends that you keep this bit set during simulation. 4–11 Description — ...

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... Table 4–11. Dynamic Reconfiguration Interface Signal Name reconfig_togxb_data[3:0] reconfig_fromgxb[67:0] 1 Dynamic reconfiguration is only supported for Stratix IV devices in the current release. Altera Transceiver PHY IP Core User Guide Direction Input Serial input data. Output Serial output data. Direction Reconfiguration signals from the Transceiver Reconfiguration IP Input core to the XAUI transceiver ...

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... This signal resets the analog CDR and deserializer logic in the RX Input channel only available in the hard IP implementation. Input PCS RX digital reset signal. Input PCS TX digital reset signal. 4–13 pll_inclk rx_cruclk PMA 3.125 Gbps serial pll_ref_clk 4 PMA 3.125 Gbps serial Description Altera Transceiver PHY IP Core User Guide ...

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... Table 4–14. Optional Control and Status Signals—Soft IP Implementation, Stratix IV GX and Stratix V Devices Signal Name rx_channelaligned rx_disperr[7:0] rx_errdetect[7:0] rx_syncstatus[7:0] Altera Transceiver PHY IP Core User Guide Direction Powers down the calibration block. A high-to-low transition on this Input signal restarts calibration. Only available in Arria II GX and Stratix IV GX, and Stratix IV GT devices. ...

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... Output rx_disperr signal to determine whether this signal indicates a code group violation or a disparity error. The rx_errdetect signal is 2 bits wide per channel for a total of 8 bits per XAUI link. 4–15 4–8. However, in some cases, Description Altera Transceiver PHY IP Core User Guide ...

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... Use this section for Stratix IV Soft XAUI ****** #create_generated_clock -name {xgmii_rx_clk_0} -source [get_pins -compatibility_mode {*alt_pma_0|alt_pma_tgx_inst|pma_direct|auto_generated|central_clk_div0|refclkout #-multiply_by 1 [get_ports {xgmii_rx_clk}] Altera Transceiver PHY IP Core User Guide Direction Indicates that the word alignment pattern programmed has been Output detected in the current word boundary. The rx_patterndetect signal is 2 bits wide per channel for a total of 8 bits per XAUI link ...

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... This .sdc file is only applicable to the XAUI IP core when compiled in isolation. You can use reference to help in creating your own .sdc file. December 2010 Altera Corporation 4–17 Altera Transceiver PHY IP Core User Guide ...

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... Altera Transceiver PHY IP Core User Guide Chapter 4: XAUI PHY IP Core TimeQuest Timing Constraints December 2010 Altera Corporation ...

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... Interlaken is a high speed serial communication protocol for chip-to-chip packet transfers. The Altera Interlaken PHY IP core implements Specification, Rev up to 10.3125 Gbps on Stratix V devices. The key advantage of Interlaken is its low I/O count compared to earlier protocols such as SPI 4.2. Other key features include flow control, low overhead framing, and extensive integrity checking ...

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... Preliminary support—Verified with preliminary timing models for this device. Table 5–1 shows the level of support offered by the Interlaken PHY IP core for Altera device families Table 5–1. Device Family Support Stratix V devices–hard PCS + hard PMA Other device families Performance and Resource Utilization Table 5– ...

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... When selected rx_coreclkin is available as input port which drives the read side of RX FIFO, When deselected, an internal state machine takes control. rx_user_clkout (which is a master rx_clockout) drives the RX read side of FIFO. rx_user_clkout is also available as an output port. Altera Transceiver PHY IP Core User Guide 5–3 ...

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... Table 5–4. Avalon-ST TX Signals Signal Name Direction Sink tx_parallel_data[63:0] Sink tx_parallel_data[64] Sink tx_parallel_data[65] Source tx_ready Source tx_datain_bp Altera Transceiver PHY IP Core User Guide Component Interface Tcl Reference (Note 1) Interlaken Top-Level Signals tx_parallel_data<n>[65:0] tx_serial_data<n> tx_ready rx_serial_data<n> tx_datain_bp<n> tx_clkout<n> tx_user_clkout rx_parallel_data<n>[71:0] rx_ready rx_clkout< ...

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... The RX interface has a ready latency of 1 cycle so that Sink rx_dataout<n>[63:0] and rx_ctrlout are valid the cycle after rx_dataout_bp<n> is asserted. Master channel rx_clkout is available when you do not create the Output optional rx_coreclkin. 5–5 Description Altera Transceiver PHY IP Core User Guide ...

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... RW reset_ch_bitmask W reset_control (write) 0x042 [1:0] R reset_status(read) Altera Transceiver PHY IP Core User Guide Direction Input Avalon-MM clock input. Global reset signal that resets the entire interlaken PHY. A positive Input edge on this signal triggers the reset controller. Input 9-bit Avalon-MM address. Input Input data ...

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... RX data, and that the RX CDR has changed from LTR to LTD mode. Bit <n> corresponds to channel <n>. When asserted, indicates that the RX CDR PLL is locked to the reference clock. Bit <n> corresponds to channel <n>. 5–7 Description 1–2, performs a standard Altera Transceiver PHY IP Core User Guide ...

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... Table 5–9. Serial Interface Signal Name tx_serial_data rx_serial_data Altera Transceiver PHY IP Core User Guide Stratix V Device Registers Asserted when the first alignment pattern is found. The RX FIFO generates this synchronous signal. Asserted by the frame synchronizer to indicate that 4 sync words have been identified so that the RX metaframe is synchronized ...

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... When disabled, tx_cllkout drives the write side the TX FIFO. When enabled rx_coreclkin is available as input port which drives the read side of RX FIFO. Altera recommends using this clock to Input reduce clock skew. When disabled, rx_cllkout drives the write side the RX FIFO ...

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... VHDL wrapper without purchasing a mixed-language simulator. f For more information about simulating with ModelSim, refer to the ModelSim Support Altera Transceiver PHY IP Core User Guide Description The top-level static Verilog HDL file for the Interlaken PHY IP core. It includes parameterized port widths. ...

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... Verilog variant name as generated by Qmegawiz set dut_name <top level Verilog design name> # tb_name = top-level testbench name. # Can be Verilog or VHDL depending on your Modelsim license. set tb_name <top level Verilog/VHDL testbench name> December 2010 Altera Corporation 5–11 Altera Transceiver PHY IP Core User Guide ...

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... Altera Transceiver PHY IP Core User Guide Chapter 5: Interlaken PHY IP Core Simulation Testbench December 2010 Altera Corporation ...

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... Interface for PCI Express (PIPE) Architecture connects to a PCI Express PHYMAC to create a complete PCI Express design. Altera supports the Gen1 and Gen2 specifications and ×1, ×2, ×4, or ×8 operation for a total aggregate bandwidth of 2–32 Gbps. ...

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... PIPE low latency On/Off synchronous mode PLL reference clock 100 MHz frequency 125 MHz Run length 40–160 Enable electrical idle True/False inferencing Altera Transceiver PHY IP Core User Guide Logic Registers 460 285 530 373 590 425 460 295 530 373 590 425 Table 6– ...

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... PCI Express PIPE PHY Top-Level Signals tx_serial_data[<n>-1:0] rx_serial_data[<n>-1:0] pll_locked rx_is_lockedtodata[<n>-1:0] rx_is_lockedtoref[<n>-1:0] rx_syncstatus[<d>/<n><s>-1:0] SOPC Builder User Guide. High Speed Serial I/O tx_ready rx_ready Status Altera Transceiver PHY IP Core User Guide 6–3 ...

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... It transfers commands received on its Avalon-MM slave interface to its Avalon-MM port. This interface provides access to features of the PCS and PMA that are not part of the standard PIPE interface. Altera Transceiver PHY IP Core User Guide Specifications. Dir This is TX parallel data driven from the PCI Express PHYMAC. The ready ...

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... Status System Non-PIPE Interconnect Fabric Transceiver S Reconfiguration Controller 6–5 PCI Express PIPE Hard PCS and PMA Reset Clocks Clocks Rx Data, Datak Tx Data, Datak Valid PIPE Control PIPE Status Non-PIPE Control Non-PIPE Status Dynamic Partial Reconfiguration Altera Transceiver PHY IP Core User Guide ...

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... W reset_control (write) 0x042 [1:0] R reset_status(read) Altera Transceiver PHY IP Core User Guide Input Avalon-MM clock input. Global reset signal that resets the entire PHY (PIPE). A positive edge on Input this signal triggers the reset controller. Refer to for a timing diagram illustrating the reset sequence for a duplex channel. ...

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... PCS control and status registers. For variants that stripe data across multiple lanes, this is the logical group number. For non-bonded applications, this is the logical lane number. 6–7 Description 1–2, performs a standard Altera Transceiver PHY IP Core User Guide ...

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... RW rx_bitreversal_enable [0] RW rx_enapatternalign Altera Transceiver PHY IP Core User Guide Chapter 6: PCI Express PHY (PIPE) IP Core Description — Records the number of bits slipped by the RX Word Aligner to achieve word alignment. Used for very latency sensitive protocols. From block: Word aligner. ...

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... Intel PHY Interface for PCI Express (PIPE) Architecture timing diagrams. Transmit de-emphasis selection. In PCI Express Gen2 (5 Gbps) mode it selects the transmitter de-emphasis: Sink 1'b0 ■ 1'b1: -3.5 dB ■ Description — Description for Altera Transceiver PHY IP Core User Guide 6–9 for ...

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... Table 6–8: (1) <n> is the number of lanes. The PHY (PIPE) supports ×1, ×4, ×8 operation. Altera Transceiver PHY IP Core User Guide When asserted for one cycle, sets the 8B/10B encoder output running disparity to negative. Used when transmitting the compliance pattern. Refer Sink Intel PHY Interface for PCI Express (PIPE) to section 6 ...

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... Asserted when the receiver CDR is locked to the input reference clock. Output This signal is asynchronous. Indicates presence or absence of synchronization on the RX interface. Output Asserted when word aligner identifies the word alignment pattern or synchronization code groups in the received data stream. 6–11 250 MHz (Gen1) T1 Description Signal Name Altera Transceiver PHY IP Core User Guide ...

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... For more information about simulating with ModelSim, refer to the ModelSim Support Altera provides an example Tcl script, modelsim_example_script.tcl, with the PCI Express PIPE PHY IP core to illustrate how to compile and simulate the core in ModelSim. You must edit this script to include the following information: ■ ...

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... Verilog design name> # tb_name = top-level testbench name. # Can be Verilog or VHDL depending on your Modelsim license. set tb_name <top level Verilog/VHDL testbench name> December 2010 Altera Corporation shows the part of the Tcl script that you must edit. 6–13 Altera Transceiver PHY IP Core User Guide ...

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... Altera Transceiver PHY IP Core User Guide Chapter 6: PCI Express PHY (PIPE) IP Core Simulation December 2010 Altera Corporation ...

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... The Altera Custom PHY IP core is a generic PHY that you can customize for use in Stratix V FPGAs. You can connect your application’s MAC-layer logic to the Custom PHY to transmit and receive data at rates of 0.600–8.5 Gbps. You can parameterize the physical coding sublayer (PCS) to include the functions that your application requires. The following functions are available: ■ ...

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... Preliminary support—Verified with preliminary timing models for this device. Table 7–1 shows the level of support offered by the Custom PHY IP core for Altera device families Table 7–1. Device Family Support Arria II GX Arria II GZ HardCopy IV GX Stratix IV GX Stratix V devices–hard PCS and hard PMA ...

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... When you turn this option off, the TX and RX interfaces are configured as a single data and control bus, regardless of the number of lanes. The layout and transmission of the TX and RX buses is little endian. Refer to 7–3 Description Figure 7–2. Figure 7–3. Altera Transceiver PHY IP Core User Guide ...

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... Enable manual disparity control On/Off Create optional 8B/10B status On/Off port Altera Transceiver PHY IP Core User Guide lists the settings available on the 8B/10B tab. Value Enable this option if your application requires 8B/10B encoding and decoding. This option on adds the tx_datak<n>, rx_datak<n>, and rx_runningdisp< ...

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... Word alignment pattern: Allows you to specify a word ■ alignment pattern. If you turn this option on, you can specify the run length which is the maximum legal number of contiguous 0s or 1s. Specifies the threshold for a run-length violation. 7–5 Description Altera Transceiver PHY IP Core User Guide ...

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... SKP symbols or ordered-sets when the upstream transmitter reference clock frequency is greater than the local receiver reference clock frequency. It inserts SKP symbols or ordered-sets when the local receiver reference clock frequency is greater than the upstream transmitter reference clock frequency. Altera Transceiver PHY IP Core User Guide Word Word Alignment ...

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... To perform multiple byte ordering operations, deassert and reassert rx_enabyteord. Specifies the pattern that identifies the SOP. Specifies the pad pattern that is inserted to align the SOP. 7–7 lists the settings available on the Description Table 7–7 Description Altera Transceiver PHY IP Core User Guide ...

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... Figure 7–4: (1) <n> is the number of lanes. <d> is the deserialization factor. <s> is the symbol size in bits. <p> is the number of PLLs. Altera Transceiver PHY IP Core User Guide Value Specifies the mode of operation for the deserializer which clocks in serial input data from the RX buffer using the high-speed recovered clock and deserializes it using the low-speed parallel recovered clock ...

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... Output This is the clock for the RX parallel data source interface. Data and control indicator for the source data. When 0, indicates that Source rx_parallel_data is data, when 1, indicates that rx_parallel_data is control. 7–9 Description Description Altera Transceiver PHY IP Core User Guide ...

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... Fabric Note to Figure 7–5: (1) Blocks in gray are soft logic. Blocks in white are hard logic. Altera Transceiver PHY IP Core User Guide Direction Source This status signal indicates the disparity of the incoming data. This signal is created if you turn On the Enable byte ordering block control option on the Byte Order tab ...

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... The reset affects channels enabled in the reset_ch_bitmask. Writing bit 1 initiates a RX digital reset of channels enabled in the reset_ch_bitmask. Reading bit 0 returns the status of the reset controller TX ready bit. Reading bit 1 returns the status of the reset controller RX ready bit. 7–11 Description Description Altera Transceiver PHY IP Core User Guide ...

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... R out Altera Transceiver PHY IP Core User Guide You can use the reset_fine_control register to create your own reset sequence. The reset control module, illustrated in Figure 1–1 on page reset sequence at power on and whenever the phy_mgmt_clk_reset is asserted. Bits [31:4, 0] are reserved ...

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... This is an optional clock to drive the coreclk of the RX PCS. Input This is an optional clock to drive the coreclk of the TX PCS Output Clock for TX and RX parallel data, control, and status. 7–13 Description — 7–9) is used for all data, Description Altera Transceiver PHY IP Core User Guide ...

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... Altera Transceiver PHY IP Core User Guide (Note 1) Direction Signal Name Input Receiver differential serial input data. Output Transmitter differential serial output data. ...

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... RX block slipped to achieve a deterministic latency. Table 7–16 describes the signals in the Direction Reconfiguration signals from the Transceiver Reconfiguration Sink Controller. Source Reconfiguration signals to the Transceiver Reconfiguration Controller. 7–15 Signal Name Description Altera Transceiver PHY IP Core User Guide ...

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... Altera Transceiver PHY IP Core User Guide Chapter 7: Custom PHY IP Core Interfaces December 2010 Altera Corporation ...

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... The Altera Low Latency IP core receives and transmits differential serial data, recovering the RX clock from the RX input stream. The PMA connects to a simplified PCS that whose single function doubles the width of the TX and RX datapaths. An Avalon-ST interface is used for TX and RX data for the MAC interface. An Avalon-MM interface provides access to control and status information. Figure 8– ...

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... Final support—Verified with final timing models for this device. ■ Preliminary support—Verified with preliminary timing models for this device. Table 8–1 shows the level of support offered by the PMA IP core for Altera device families. Table 8–1. Device Family Support Device Family ...

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... The Auto mode is available in the current release so that the Quartus II software determines the correct setting. Indicates the selected deserializer width. 8–3 Description illustrates. Description Altera Transceiver PHY IP Core User Guide ...

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... TRISTATE Select the receiver common 0.82V mode voltage 1.1v Altera Transceiver PHY IP Core User Guide Value Parameters for Stratix IV and Derivatives Allows you to choose a clock multiplier unit (CMU) or auxiliary transmit (ATX) PLL. The CMU PLL is designed to achieve low TX channel-to-channel skew. The ATX PLL is designed to improve jitter performance ...

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... Description tx_serial_data<n> Serial rx_serial_data<n> Data rx_clkout[<n>-1:0] Optional pll_locked[<n>-1:0] Status tx_bitslip Altera Transceiver PHY IP Core User Guide ...

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... RX interface is an Avalon-ST source. Table 8–5. Avalon-ST interface Signal Name tx_parallel_data<n>[<d-1>:0] tx_clkout[<n>-1:0] tx_ready[<n-1>:0] rx_parallel_data<n><d-1>:0] rx_ready[<n-1>:0] Altera Transceiver PHY IP Core User Guide PMA and Light-Weight PCS Tx Data Tx Parallel Data to MAC Rx Data Rx Parallel Data Channel ...

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... RX data, and that the RX CDR has changed from LTR to LTD mode. Bit <n> corresponds to channel <n>. When asserted, indicates that the RX CDR PLL is locked to the reference clock. Bit <n> corresponds to channel <n>. 8–7 Description Description Altera Transceiver PHY IP Core User Guide ...

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... Note to Table 8–9: (1) <n> is the number of modules connecting to the Transceiver Reconfiguration IP core. Altera Transceiver PHY IP Core User Guide Direction Description Sink Differential high speed input serial data. Source Differential high speed output serial data. Direction ...

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... You can use the Altera Transceiver Reconfiguration Controller to dynamically reconfigure the TX and RX analog settings in Stratix IV GX devices. This modules is included in the Transceiver Toolkit, the XAUI PHY IP core, and the 10GBASE-R PHY IP core. Figure 9–1 Controller Stratix IV devices, the PCI Express IP core uses a different reconfiguration IP core. ...

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... Reserved 0x10B [4:0] RW tx_rx_word_offset Altera Transceiver PHY IP Core User Guide which illustrates the critical signals for the reset of a Register Name The logical channel address. Must be specified when performing dynamic updates. The physical channel address. Error. When asserted, indicates an error. This bit is asserted if any of the following conditions occur: ■ ...

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... December 2010 Altera Corporation Register Name Reconfiguration data. For complete information about the EyeQ interface and registers refer to, “EyeQ Interface Register Mapping” in the Stratix IV Dynamic Reconfiguration volume 2 of the Stratix IV Device Handbook. 9–3 Description — chapter in Altera Transceiver PHY IP Core User Guide ...

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... Altera Transceiver PHY IP Core User Guide Chapter 9: Transceiver Reconfiguration Controller Steps to Achieve PMA Controls Reconfiguration December 2010 Altera Corporation ...

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... Previously, Altera provided the ALTGX megafunction as a general purpose transceiver PHY solution. The current release of the Quartus II software includes protocol-specific PHY IP cores that simplify the parameterization process. The design of these protocol-specific transceiver PHYs is modular and uses standard interfaces. An Avalon-MM interface provides access to control and status registers that record the status of the PCS and PMA modules ...

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... Table 10–2. Correspondences between XAUI PHY Stratix IV GX and Stratix V Device Signals (Part Stratix IV GX Devices Signal Name pll_inclk rx_cruclk cal_blk_clk reconfig_clk Altera Transceiver PHY IP Core User Guide XAUI PHY Parameter Name 1000) Not available as parameters in the MegaWizard interface —Not available as parameters in the MegaWizard interface ...

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... Width 1 — [3:0] [63:0] [63:0] [3:0] — — — — — — — — — — — [<n>*2 – 1:0] — — — [<n>*2 – 1:0] [<n>*2 – 1:0] — — — — — — Altera Transceiver PHY IP Core User Guide ...

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... Starting Channel Number Enable low latency sync Enable RLV with run length of Enable electrical idle inference functionality — Altera Transceiver PHY IP Core User Guide Chapter 10: Migrating from Stratix IV to Stratix V Width Signal Name Transceiver Reconfiguration 1 Not available [3:0] ...

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... Not available in MegaWizard Interface Stratix V Device Signal Name Reference Clocks and Resets pll_ref_clk Not available Not available Not available pipe_pclk 10–5 Comments Use assignment editor to make these assignments Width 1 [<n>-1:0] [<n>-1:0] [<n>-1:0] 1 Altera Transceiver PHY IP Core User Guide ...

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... Altera Transceiver PHY IP Core User Guide Chapter 10: Migrating from Stratix IV to Stratix V Stratix V Device Signal Name Refer to the “Avalon-MM PHY Management Interface” on page 6–6 and “PCI Express PHY (PIPE) IP Core Registers” on page 6–6 ...

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... Width [<n>-1:0] [<n>-1:0] [<n>-1:0] [(<d>/8)*<n>-1:0] [(<d>/8)*<n>-1:0] [(<d>/8)*<n>-1:0] [<n>-1:0] [<n>-1:0] [<n>-1:0] [<n>-1:0] [<n>-1:0] [<n>-1: [3:0] [16: [8:0] 1 [31:0] 1 [31:0] Altera Transceiver PHY IP Core User Guide ...

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... Protocol Settings—Rate match/Byte order What is the byte ordering pattern Note to Table 10–5: (1) This parameter is on the Datapath tab. Altera Transceiver PHY IP Core User Guide Chapter 10: Migrating from Stratix IV to Stratix V Custom PHY Parameter Name General Number of lanes Bonded group size in lanes (1–5) ...

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... Avalon-ST Tx Interface Avalon-ST Rx Interface High Speed Serial I/O 10–9 Width [<p>-1:0] [<d><n>-1:0] [<d><n>-1:0] [<d><n>-1:0] [<d><n>-1:0] [<d/8><n>-1:0] [<n>-1:0] [<n>-1:0] [<n>-1:0] [<n>-1:0] Altera Transceiver PHY IP Core User Guide ...

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... Altera Transceiver PHY IP Core User Guide Chapter 10: Migrating from Stratix IV to Stratix V Custom PHY December 2010 Altera Corporation ...

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... This chapter provides additional information about the document and Altera. Revision History The table below displays the revision history for the chapters in this user guide. Date Version Corrected frequency range for the phy_mgmt_clk for the Custom PHY IP core in ■ on page Added optional reconfig_fromgxb[67:0] to ■ ...

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... Revised register map to show word addresses instead of a byte offset from a base address. ■ December Changed phy_mgmt_address from bits. ■ 1.1 2010 Altera Transceiver PHY IP Core User Guide Changes Made Interlaken PHY Transceiver Figure 5–2 on page PCI Express PHY (PIPE) Custom PHY Transceiver and subsequent signal descriptions. ...

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... Technical training Product literature Non-technical support (General) (Software Licensing) Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Bold Type with Initial Capital ...

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... A warning calls attention to a condition or possible situation that can cause you injury. The envelope links to the Email Subscription Management Center website, where you can sign up to receive update notifications for Altera documents. Additional Information Typographic Conventions page on the Altera December 2010 Altera Corporation ...