IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 5

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Revision History
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2.1.1
2.1.0
2.0.0
1.0.0
Version
Table 2. PCI Express Compiler Revision History
June 2006
April 2006
October 2005
April 2005
Date
The following enhancemnets were made:
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Table 2
2.1.1.
Copyright © 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company,
the stylized Altera logo, specific device designations, and all other words and logos that are identified as
trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their re-
spective holders. Altera products are protected under numerous U.S. and foreign patents and pending
applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products
to current specifications in accordance with Altera's standard warranty, but reserves the right to make chang-
es to any products and services at any time without notice. Altera assumes no responsibility or liability
arising out of the application or use of any information, product, or service described
herein except as expressly agreed to in writing by Altera Corporation. Altera customers
are advised to obtain the latest version of device specifications before relying on any pub-
lished information and before placing orders for products or services
The Stratix II GX ALT2GXB Vod/pre-emphasis settings changed to improve the
margins in meeting the Transmitter Compliance Eye Diagram.
PHY Support logic provides better timing margins in Cyclone II devices.
The example design DMA now handles out-of-order read completions.
The AER Header Log registers have been enhanced for PCI-SIG read only
compliance test
The <variation>_phy_support module added cfg_msicsr, cfg_pmcsr, adn
cfg_prmcsr ports.
Example design now sends the correct completion for zero length read requests.
Additional Transaction layer support for x1 MegaCore function to operate at 62.5
MHz or 125 MHz.
Added support for Advanced Error Reporting (AER) and ECRC generation and
checking in the x8 MegaCore function (previously only supported in x4 and x1)
Additional Rx Buffer configuration options that optimize your application’s
performance with minimal resource utilization.
Enhanced flow control algorithmimproves throughput when both PCI Express
link directions are heavily loaded
Support additional custom external PHY modes
Support for compliance with PCI Express Specification v1.1
Added Stratix II GX, HardCopy II, and Cylcone II device support
Added x8 support
Initial Publication
shows the revision history for the PCI Express Compiler version
Revision
.
Revision History
Preliminary
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