IPR-POSPHY4 Altera, IPR-POSPHY4 Datasheet - Page 5

• Manufacturer Part Number: IPR-POSPHY4
• Description: IP CORE Renewal Of IP-POSPHY4
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

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2.3.1
2.3.0
Version
Table 2. POS-PHY Level 4 MegaCore Function v2.4.1 Revision History (Part 2 of 2)
April 2005
February 2005
Date
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Copyright © 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company,
the stylized Altera logo, specific device designations, and all other words and logos that are identified as
trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their re-
spective holders. Altera products are protected under numerous U.S. and foreign patents and pending
applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products
to current specifications in accordance with Altera's standard warranty, but reserves the right to make chang-
es to any products and services at any time without notice. Altera assumes no responsibility or liability
arising out of the application or use of any information, product, or service described
herein except as expressly agreed to in writing by Altera Corporation. Altera customers
are advised to obtain the latest version of device specifications before relying on any pub-
lished information and before placing orders for products or services
ALTLVDS instances can be edited with the ALTLVDS Megafunction wizard.
Relaxed restrictions on calendar length and calendar multiplier.
Cyclone™ II device family support at up to 250 Mbps.
Asymmetric ports and hitless bandwidth reprovisioning.
Re-architected clock-domain crossing and Atlantic
significantly reducing the logic consumption for 64- and 128-bit receiver
variations.
Option to select single or multiple clock domain Atlantic buffering.
Optional Atlantic interface width.
Optional parity protection across Atlantic first-in first-out (FIFO) buffer
memories.
Revision
.
™
alignment blocks,
Revision History
Preliminary
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