CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 10
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CDB42L52
Manufacturer Part Number
CDB42L52
Description
Eval Bd LP Codec W/Class D Spkr Driver
Manufacturer
Cirrus Logic Inc
Specifications of CDB42L52
Main Purpose
Audio, CODEC
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
CS42L52
Primary Attributes
4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
Secondary Attributes
GUI, I2C, SPI, USB Interfaces
Description/function
Audio CODECs
Operating Supply Voltage
5 V
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
CS42L52
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
598-1505
CDB42L52
2.4
DSP Engine Tab
The “DSP Engine” tab provides high-level control of the SDIN (PCM) data volume level, the ADC out-
put/SDIN mix volume level and the overall DAC/PWM channel volume level. DAC/PWM channel Limiter,
Tone Control and Beep Generator control functions are also provided. Status text detailing the CODEC’s
specific configuration is shown in parenthesis or inside the control group of the affected control. This text
will change depending on the setting of the associated control. A description of each control group is out-
lined below (a description of each register is included in the CS42L52 data sheet):
Digital Volume Control - Digital volume controls and adjustments for the SDIN data, ADC out data and over-
all channel volume. Mute, gang, invert and de-emphasis functions are also available.
Limiter - Configuration settings for the Automatic Level Control (ALC).
Tone Control - Bass and treble volume controls and filter corner frequencies.
Beep Generator - On/Off time, frequency, volume, mix and repeat beep functions.
Update - Reads all registers in the CS42L52 and reflects the current values in the GUI.
Reset - Resets the CS42L52.
Figure 4. ADC Channel Volume Tab
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DS680DB1