CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 2

• Manufacturer Part Number: CDB42L52
• Description: Eval Bd LP Codec W/Class D Spkr Driver
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L52

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L52
• Primary Attributes: 4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
• Secondary Attributes: GUI, I2C, SPI, USB Interfaces
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42L52
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1505

2
TABLE OF CONTENTS
LIST OF FIGURES
LIST OF TABLES
1. SYSTEM OVERVIEW ............................................................................................................................. 3
2. SOFTWARE MODE CONTROL ............................................................................................................. 6
3. SYSTEM CONNECTIONS AND JUMPERS ........................................................................................ 13
4. CDB42L51 SCHEMATICS ................................................................................................................... 17
5. CDB42L51 LAYOUT ............................................................................................................................ 21
6. REVISION HISTORY ............................................................................................................................ 26
Figure 1.Board Configuration Tab ............................................................................................................... 7
Figure 2.CODEC Configuration Tab ........................................................................................................... 8
Figure 3.ADC Channel Volume Tab ............................................................................................................ 9
Figure 4.ADC Channel Volume Tab .......................................................................................................... 10
Figure 5.Analog and PWM Output Volume Tab ........................................................................................ 11
Figure 6.Register Maps Tab - CS42L52 ................................................................................................... 12
Figure 7.Block Diagram ............................................................................................................................. 16
Figure 8.CS42L52 & Analog I/O (Schematic Sheet 1) .............................................................................. 17
Figure 9.S/PDIF & Digital Interface (Schematic Sheet 2) ......................................................................... 18
Figure 10.Micro & FPGA Control (Schematic Sheet 3) ............................................................................. 19
Figure 11.Power (Schematic Sheet 4) ...................................................................................................... 20
Figure 12.Silk Screen ................................................................................................................................ 21
Figure 13.Top-Side Layer ......................................................................................................................... 22
Figure 14.GND (Layer 2) ........................................................................................................................... 23
Figure 15.Power (Layer 3) ........................................................................................................................ 24
Figure 16.Bottom Side Layer .................................................................................................................... 25
Table 1. System Connections ................................................................................................................... 13
Table 2. Jumper Settings .......................................................................................................................... 14
1.1 Power ............................................................................................................................................... 3
1.2 Grounding and Power Supply Decoupling ....................................................................................... 3
1.3 FPGA ............................................................................................................................................... 3
1.4 CS42L52 Audio CODEC .................................................................................................................. 3
1.5 CS8406 Digital Audio Transmitter .................................................................................................... 4
1.6 CS8416 Digital Audio Receiver ........................................................................................................ 4
1.7 Oscillator .......................................................................................................................................... 4
1.8 I/O Stake Headers ........................................................................................................................... 4
1.9 Analog Inputs ................................................................................................................................... 5
1.10 Analog Outputs .............................................................................................................................. 5
1.11 Control Port Connectors ................................................................................................................ 5
2.1 Board Configuration Tab .................................................................................................................. 7
2.2 CODEC Configuration Tab .............................................................................................................. 8
2.3 Analog Input Volume Tab ................................................................................................................ 9
2.4 DSP Engine Tab ............................................................................................................................ 10
2.5 Analog and PWM Output Volume Tab ........................................................................................... 11
2.6 Register Maps Tab ......................................................................................................................... 12
1.11.1 USB Connector ..................................................................................................................... 5
CDB42L52
DS680DB1