JN5148/001,518 NXP Semiconductors, JN5148/001,518 Datasheet - Page 24

• Manufacturer Part Number: JN5148/001,518
• Description: MCU 802.15.4 32BIT 2.4G 56-QFN
• Manufacturer: NXP Semiconductors
• Series: JN5148r

Specifications of JN5148/001,518

• Frequency: 2.4GHz
• Data Rate - Maximum: 667kbps
• Modulation Or Protocol: 802.15.4
• Applications: Home/Building Automation, Industrial Control
• Power - Output: 2.5dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2 V ~ 3.6 V
• Current - Receiving: 17.5mA
• Current - Transmitting: 15mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB RAM, 128kB ROM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-VFQFN
• Core: RISC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7 Interrupt System
The interrupt system on the JN5148 is a hardware-vectored interrupt system. The JN5148 provides several interrupt
sources, some associated with CPU operations (CPU exceptions) and others which are used by hardware in the
device. When an interrupt occurs, the CPU stops executing the current program and loads its program counter with a
fixed hardware address specific to that interrupt. The interrupt handler or interrupt service routine is stored at this
location and is run on the next CPU cycle. Execution of interrupt service routines is always performed in supervisor
mode. Interrupt sources and their vector locations are listed in Table 2 below:
7.1 System Calls
The b.trap and b.sys instructions allow processor exceptions to be generated by software.
A system call exception will be generated when the b.sys instruction is executed. This exception can, for example, be
used to enable a task to switch the processor into supervisor mode when a real time operating system is in use. (See
section 3 for further details.)
The b.trap instruction is commonly used for trapping errors and for debugging.
7.2 Processor Exceptions
7.2.1 Bus Error
A bus error exception is generated when software attempts to access a memory address that does not exist, or is not
populated with memory or peripheral registers or when writing to ROM.
7.2.2 Alignment
Alignment exceptions are generated when software attempts to access objects that are not aligned to natural word
boundaries. 16-bit objects must be stored on even byte boundaries, while 32-bit objects must be stored on quad byte
boundaries. For instance, attempting to read a 16-bit object from address 0xFFF1 will trigger an alignment exception
as will a read of a 32-bit object from 0xFFF1, 0xFFF2 or 0xFFF3. Examples of legal 32-bit object addresses are
0xFFF0, 0xFFF4, 0xFFF8 etc.
7.2.3 Illegal Instruction
If the CPU reads an unrecognised instruction from memory as part of its instruction fetch, it will cause an illegal
instruction exception.
7.2.4 Stack Overflow
When enabled, a stack overflow exception occurs if the stack pointer reaches a programmable location.
24
Interrupt Source
Bus error
Tick timer
Alignment error
Illegal instruction
Hardware interrupt
System call
Trap
Reset
Stack Overflow
Vector Location
0x08
0x0e
0x14
0x1a
0x20
0x26
0x38
0x3e
0x2c
Interrupt Definition
Typically cause by an attempt to access an invalid address or a
disabled peripheral
Tick timer interrupt asserted
Load/store address to non-naturally-aligned location
Attempt to execute an unrecognised instruction
interrupt asserted
System call initiated by b.sys instruction
caused by the b.trap instruction or the debug unit
Caused by software or hardware reset.
Stack overflow
Table 2: Interrupt Vectors
JN-DS-JN5148-001 1v6
© NXP Laboratories UK 2010