PN5120A0HN1/C2,151 NXP Semiconductors, PN5120A0HN1/C2,151 Datasheet - Page 71
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PN5120A0HN1/C2,151
Manufacturer Part Number
PN5120A0HN1/C2,151
Description
IC TRANSMISSION MOD 32-HVQFN
Manufacturer
NXP Semiconductors
Specifications of PN5120A0HN1/C2,151
Rf Type
Read / Write
Frequency
13.56MHz
Features
ISO14443-A, ISO14443-B
Package / Case
32-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PN5120A0HN1/C2,151
Manufacturer:
NXP/恩智浦
Quantity:
20 000
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NXP Semiconductors
111334
Product data sheet
10.4.2 Data validity
10.4.3 START and STOP conditions
Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH or
LOW state of the data line shall only change when the clock signal on SCL is LOW.
To handle the data transfer on the I
are defined.
A START condition is defined with a HIGH to LOW transition on the SDA line while SCL is
HIGH.
A STOP condition is defined with a LOW to HIGH transition on the SDA line while SCL is
HIGH.
The master always generates the START and STOP conditions. The bus is considered to
be busy after the START condition. The bus is considered to be free again a certain time
after the STOP condition.
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In
this respect, the START (S) and repeated START (Sr) conditions are functionally identical.
Fig 18. Bit transfer on the I
Fig 19. START and STOP conditions
Rev. 3.4 — 8 September 2009
2
C-bus
2
C-bus, unique START (S) and STOP (P) conditions
Transmission Module
© NXP B.V. 2010. All rights reserved.
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