PN5120A0HN1/C2,151 NXP Semiconductors, PN5120A0HN1/C2,151 Datasheet - Page 91

• Manufacturer Part Number: PN5120A0HN1/C2,151
• Description: IC TRANSMISSION MOD 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN1/C2,151

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
13. Timer unit
111334
Product data sheet
A timer unit is implemented in the PN512. The external host controller may use this timer
to manage timing relevant tasks. The timer unit may be used in one of the following
configurations:
The timer unit can be used to measure the time interval between two events or to indicate
that a specific event occurred after a specific time. The timer can be triggered by events
which will be explained in the following, but the timer itself does not influence any internal
event (e.g. A time-out during data reception does not influence the reception process
automatically). Furthermore, several timer related bits are set and these bits can be used
to generate an interrupt.
Timer
The timer has an input clock of 13.56 MHz (derived from the 27.12 MHz quartz). The timer
consists of two stages: 1 prescaler and 1 counter.
The prescaler is a 12-bit counter. The reload value for TPrescaler can be defined between
0 and 4095 in register TModeReg and TPrescalerReg.
The reload value for the counter is defined by 16 bits in a range of 0 to 65535 in the
register TReloadReg.
The current value of the timer is indicated by the register TCounterValReg.
If the counter reaches 0 an interrupt will be generated automatically indicated by setting
the TimerIRq bit in the register CommonIRqReg. If enabled, this event can be indicated on
the IRQ line. The bit TimerIRq can be set and reset by the host controller. Depending on
the configuration the timer will stop at 0 or restart with the value from register
TReloadReg.
The status of the timer is indicated by bit TRunning in register Status1Reg.
The timer can be manually started by TStartNow in register ControlReg or manually
stopped by TStopNow in register ControlReg.
Furthermore the timer can be activated automatically by setting the bit TAuto in the
register TModeReg to fulfill dedicated protocol requirements automatically.
The time delay of a timer stage is the reload value +1.
The definition of total time is: t = ((TPrescaler*2+1)*TReload+1)/13.56MHz
Maximum time:
Example:
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To indicate 25 us it is required to count 339 clock cycles. This means the value for
TPrescaler has to be set to TPrescaler = 169.The timer has now an input clock of 25 us.
The timer can count up to 65535 timeslots of each 25 μs.
Time-out counter
Watch-dog counter
Stop watch
Programmable one-shot
Periodical trigger
TPrescaler = 4095,TReloadVal = 65535
=> (2*4095 +1)*65536/13.56 MHz = 39.59 s
Rev. 3.4 — 8 September 2009
Transmission Module
© NXP B.V. 2010. All rights reserved.
PN512
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