IP4252CZ16-8-TTL NXP Semiconductors, IP4252CZ16-8-TTL Datasheet - Page 9

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IP4252CZ16-8-TTL

Manufacturer Part Number
IP4252CZ16-8-TTL
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of IP4252CZ16-8-TTL

Operating Temperature Min Deg. C
-40C
Operating Temperature Max Deg. C
85C
Rad Hardened
No
Lead Free Status / RoHS Status
Compliant

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NXP Semiconductors
IP4251_52_53_54-TTL
Objective data sheet
7.2.1 SDHC and MMC memory interface
7.2 Selection
The selection of one of the filter devices has to be performed depending on the maximum
clock frequency, driver strength, capacitive load of the sink, and also the maximum
applicable rise and fall times.
The Secure Digital High Capacity (SDHC) memory card interface standard specification
and the Multi Media Card (MMC) (JESD 84A43) standard specification recommend a rise
and fall time of 25 % to 62.5 % (62.5 % to 25 % respectively) of 3 ns or less for the input
signal of the receiving interface side.
Assuming a typical capacitance of about 20 pF for the SDHC memory card itself, and
approximately 4 pF to 7 pF for the Printed-Circuit Board (PCB) and the card holder,
IP4252CZ12-6-TTL (6 channels, R
matching selection to filter and protect all relevant interface pins such as CLK, CMD, and
DAT0 to DAT3/CD. Please refer to
of the device in an SDHC card interface.
In case additional channels such as write-protect or a mechanical card-detection switch
are used, the IP4252CZ16-8-TTL (8 channels, R
V
bias(DC)
= 2.5 V) offers two additional channels.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 31 January 2011
Integrated 4-, 6- and 8-channel passive filter network
s(ch)
Figure 7
= 40 Ω, C
for a general example of the implementation
IP4251/52/53/54-TTL
s(ch)
ch
= 12 pF at V
= 40 Ω, C
ch
bias(DC)
= 12 pF at
= 2.5 V) is a
© NXP B.V. 2011. All rights reserved.
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