NCP1608BDR2G ON Semiconductor, NCP1608BDR2G Datasheet - Page 16

• Manufacturer Part Number: NCP1608BDR2G
• Description: IC PFC CTLR/PRECONVERTER 8-SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1608BDR2G

• Mode: Critical Conduction (CRM)
• Frequency - Switching: Adjustable
• Current - Startup: 24µA
• Voltage - Supply: 8.8 V ~ 12.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Switching Frequency: 70 KHz
• Maximum Power Dissipation: 450 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

through the path shown in Figure 35.
MOSFET, the diode, and the inductor. C
energy discharged by C
reverse biases the bridge rectifier and causes the input
current (I
causes THD to increase. To reduce THD, the ratio (t
is minimized, where t
when the drive turns on. The ratio (t
proportional to the square root of L.
and no voltage signal to activate the ZCD comparators.
This means that the drive never turns on. To enable the PFC
stage to start under these conditions, an internal watchdog
timer (t
turns the drive on if the drive has been off for more than
165 ms (typical value). This feature is deactivated during a
fault mode (OVP or UVP), and reactivated when the fault
is removed.
Wide Control Range
output power is decreased from the maximum output
power to the minimum output power in the application. In
high power applications (>150 W), V
a low voltage at a large output power and Ct
constant. The result is that V
voltage at a large output power. The low V
V
power combined with the low V
the probability of noise interfering with the control signals
and on time duration (Figures 36 and 37). The noise induces
voltage spikes on the Control pin and Ct pin that reduces the
drive on time from the on time determined by the feedback
loop (t
Ct(off)
During the delay caused by R
C
During startup, there is no energy in the ZCD winding
The Ct charging threshold (V
EQ(drain)
on(loop)
voltages are susceptible to noise. The large output
start
AC Line
in
) to decrease to zero. The zero input current
) is integrated into the controller. This timer
is the combined parasitic capacitances of the
). The reduced on time causes the energy
I
in
Z
is the period from when I
Filter
EMI
EQ(drain)
Ct(off)
Figure 35. Equivalent Drain Capacitance Discharge Path
Control
ZCD
Ct(off)
. The charging of C
and the ZCD pin capacitance, the equivalent drain capacitance (C
z
is reduced to a low
Control
and V
/ T
) decreases as the
in
+
is charged by the
SW
C
(offset)
Ct(off)
in
) is inversely
is reduced to
Control
L
= 0 A to
increase
remains
z
http://onsemi.com
/ T
L
I
L
SW
and
in
)
16
stored in the inductor (L) to be reduced. The result is that
V
until t
and reduced power factor.
ZCD
V
V
ZCD(ARM)
V
ZCD(TRIG)
Ct
V
CL(NEG)
Figure 36. Control Pin Noise Induced On Time
V
start
Control
does not exceed V
(offset)
Ct(off)
V
DRV
ZCD
V
Ct
expires. This sequence results in pulse skipping
Reduction and Pulse Skipping
t
on(loop)
t
on
C
EQ(drain)
ZCD(ARM)
D
Noise Induced Voltage Spike
DRV Remains Off
is Not Exceeded
V
+
ZCD(ARM)
t
C
start
and the drive remains off
bulk
V
Low V
Low V
out
EQ(drain)
V
Control
Control
Ct(off)
) discharges
− Ct
Voltage
Voltage
(offset)
0 V