CRD-49530-USB Cirrus Logic Inc, CRD-49530-USB Datasheet - Page 35

• Manufacturer Part Number: CRD-49530-USB
• Description: Audio Modules & Development Tools Eval Bd 32-Bit Aud Dcdr & Prgrmble DSP
• Manufacturer: Cirrus Logic Inc

Specifications of CRD-49530-USB

• Product: Audio Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS705RD3
5.2.3 Memory
5.2.4 S/PDIF Receiver
The input and output audio clocking domains are separated. This allows the DSP to accept audio in one
Fs and produce output samples at a different sample rate such as 2Fs or 4Fs. The CS4953xx is slave
only on the input clock domain (MUXED_SCLK, MUXED_LRCLK). On the audio outputs, the CS4953xx is
slave-only for the MUXED_MCLK master audio clock, and master-only for DSP_SCLK and DSP_LRCLK
which are used to shift data out of the CS4953xx.
The CRD USB Master USB board acts as the host controller in the CRD49530 platform, and is connected
to the CRD49530 via J11 on page 8 of the schematics. The CRD USB Master drives several DSP
interfaces including the serial host control port (SCP1), the debug port, and DSP_RESET. The CRD USB
Master also controls the multiplexer (ADC/HDMI_SEL) that selects the I
CS4953xx.
Figure 5-3
with 4 Mbit of serial flash on-board. Both standard serial flash footprints are supported in this design, and
this is shown in the schematic as two different serial flash devices. By default, only the SST flash (U13) is
populated
The CRD49530 is populated with a 64 Mbit, 166 MHz SDRAM with a 16-bit-wide data bus (U7). Note that
both the series termination (R40) and the parallel termination (R42) for SD_CLKIN are physically close to
the DSP on the board. Both termination options were designed into the CRD49530, but only the parallel
termination is being used on this board, so the series terminator (R40) is populated with a 0-ohm resistor.
The parallel flash (U6) is not populated. serial Flash is recommended for all CS4953xx systems, as it
makes layout of the SDRAM interface much simpler, but the parallel flash footprint has been included as
an option.
Figure 5-4
rates up to 192 kHz.
The serial host control port (SCL/CCLK, SDA/CDOUT, AD1/CDIN, AD0/CS) shares clock and data lines
with the CS4953xx and CS42448. The CS8416_CS line is unique to this chip and driven only when in SPI
mode. The pull-ups required for the SCL and SDA pins are shared with the other devices on the
CRD49530 board.
The BRD_RST signal is a shared reset signal.
The reference clock for the CS8416 is the XTAL_OUT (buffered 24.576 MHz crystal) output from the
CS4953xx.
The CS8416_MCLK signal is the master audio clock for on-board audio sources. This clock can be either
an MCLK recovered from a S/PDIF stream or the XTAL_OUT reference, depending on the setting of the
CS8416’s internal multiplexer.
The CS8416 is master only for the CS8416_MCLK signal, which is one possible source for the
MUXED_MCLK master audio clock.
The CS8416 slaves to the CS8416_SCLK and CS8416_LRCLK signals which are used to shift I
out of the CS8416 and shift I
Note: SA_BA1 is the default bank address for 16-Mbit SDRAM designs. SD_BA1 and SD_BA0 are
swapped in the CRD49530-USB design to allow for the evaluation of both 16-Mbit and 64 M-bit
designs. SD_BA1 and SD_BA0 do not need to be swapped for 64-Mbit designs.
shows the schematic for the SDRAM and Flash memory blocks. The CRD49530 was designed
shows the schematic for the CS8416, which is a S/PDIF receiver capable of supporting sample
2
S data into the CS4953xx.
Copyright 2008 Cirrus Logic
2
S audio input lines for the
Detailed Schematic Descriptions
CRD49530-USB User’s Manual
2
S data
5-2