ATDS94KSW2 Atmel, ATDS94KSW2 Datasheet - Page 2

• Manufacturer Part Number: ATDS94KSW2
• Description: Development Software SYSTEM DESIGN. SOFT- WARE FOR FPSLIC
• Manufacturer: Atmel

Specifications of ATDS94KSW2

• Tool Function: Compiler
• Tool Type: Compiler
• Processor Series: AT94K/AT94S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

System Designer
Desktop
Design Flow View
FPGA Flow
AVR Flow
2
System Designer
The System Designer desktop is shown in Figure 1. The Design Flow chart on the right
provides push-button access to all the stages in a typical design flow. This includes
code entry, software debugging (Figure 2), simulation (Figure 3), synthesis (Figure 4)
and generating files for simulations automatically. The FPGA Place and Route is
described in Figure 5, Figure 6 and Figure 7 and the AVR
in Figure 8.
Figure 1. System Designer Desktop
The Design Flow view shows the steps required to create a design for FPSLIC devices
using System Designer and Co-verification. The arrows on the diagram show depen-
dencies between the steps. The Flow view consists of two flows: FPGA flow and AVR
flow. The System Level Integration flow is used for co-verification, see “Co-verification”
on page 4. Designers can use the Coverification flow or may prefer to run the FPGA flow
and the AVR flow stand-alone, and then merge the design at the end. In this case, the
AVR designer and the FPGA designer have to agree on which parts of the design will be
done in the AVR and which will be done in the FPGA. Then define the signals between
the 2 devices.
To run the FPGA flow a test bench has to emulate the AVR side of the design to
progress with the FPGA part of the design independently from the AVR progress. The
only dependency into the FPGA flow is that the AVR FPGA interface section has to be
run. This defines the connections from the FPGA to the AVR and provides the correct
layout to optimize timing in design. If this dependency is not completed, the design will
run as if it was a stand-alone FPGA with all the inputs being provided externally.
The designer will develop the AVR function and use the normal AVR design flow with a
compiler and debugger. This can either be done within System Designer or externally
using IAR Workbench or Standalone AVR Studio.
®
-FPGA Interface is described
2307D–03/03