71M6521DEIM-DB Maxim Integrated Products, 71M6521DEIM-DB Datasheet - Page 103

• Manufacturer Part Number: 71M6521DEIM-DB
• Description: Power Management Modules & Development Tools 71M6521DE DEMO BOARD M6521DE DEMO BOARD
• Manufacturer: Maxim Integrated Products

Specifications of 71M6521DEIM-DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

71M652X Software User’s Guide
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.
Memory organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas:
program memory (External Flash), external data memory (External RAM), and internal data memory (Internal RAM).
The 80515 can address up to 64kB of program memory space from 0000H to FFFFH. Program memory is read when
the MPU fetches instructions or performs a MOVC.
After reset, the MPU starts program execution from location 0000H. The lower part of the program memory includes a
reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting from 0003H.
The 80515 can address up to 64kB of external data memory in the space from 0000H to FFFFH. The 80515 writes into
external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The external data
memory is read when the MPU executes a MOVX A,@Ri or MOVX A,@DPTR instruction.
There is an improved variable length access for the MOVX instructions to access fast or slow external RAM and
external peripherals. The three low ordered bits of the CKCON register define the stretch memory cycles. Setting all the
CKCON stretch bits to one allows access to very slow external RAM or external peripherals.
Table 6-2 shows how the signals of the External Memory Interface change when stretch values are set from 0 to 7. The
widths of the signals are counted in MPU clock cycles. The post-reset state of the CKCON register, which is in bold in
the table, performs the MOVX instructions with a stretch value equal to 1.
Revision 1.7
6.2
6.2.1 Memory organization
80515 ARCHITECTURAL OVERVIEW
Program Memory
External Data Memory
C 000H
FFFFH
8000H
4000H
0000H
Program m em ory
© Copyright 2005-2007 TERIDIAN Semiconductor Corporation
Figure 6-1: Memory Map
TERIDIAN Proprietary
C 000H
FFFFH
8000H
4000H
0000H
External data m em ory
FFH
00H
Internal data m em ory
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