LC4064ZE-EVN Lattice, LC4064ZE-EVN Datasheet - Page 33

• Manufacturer Part Number: LC4064ZE-EVN
• Description: MCU, MPU & DSP Development Tools ispMACH4064ZE Eval board
• Manufacturer: Lattice

Specifications of LC4064ZE-EVN

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Signal Descriptions
ORP Reference Table
Number of I/Os
Number of GLBs
Number of
I/Os per GLB
Reference ORP
Table (I/Os per
GLB)
TMS
TCK
TDI
TDO
GOE0/IO, GOE1/IO
GND
NC
V
CLK0/I, CLK1/I, CLK2/I, CLK3/I
V
yzz
1. In some packages, certain I/Os are only available for use as inputs. See the Logic Signal Connections tables for details.
CC
CCO0
, V
CCO1
Signal Names
4032ZE
32
16
16
2
32
4
8
8
Input – This pin is the IEEE 1149.1 Test Mode Select input, which is used to control
Input – This pin is the IEEE 1149.1 Test Data In pin, used to load data.
These pins are configured to be either CLK input or as an input.
the state machine.
Input – This pin is the IEEE 1149.1 Test Clock input pin, used to clock through the
state machine.
Output – This pin is the IEEE 1149.1 Test Data Out pin used to shift data out.
These pins are configured to be either Global Output Enable Input or as general I/O
pins.
Ground
Not Connected
The power supply pins for logic core and JTAG port.
The power supply pins for each I/O bank.
Input/Output
reference (alpha) and z is macrocell reference (numeric). z: 0-15.
Mixture of
4064ZE
14, 15
14, 15
9, 10,
9, 10,
48
4
ispMACH 4032ZE
ispMACH 4064ZE
ispMACH 4128ZE
ispMACH 4256ZE
1
– These are the general purpose I/O used by the logic array. y is GLB
64
16
16
4
33
64
8
8
8
4128ZE
ispMACH 4000ZE Family Data Sheet
Description
96
12
12
8
64
16
4
4
y: A-B
y: A-D
y: A-H
y: A-P
4256ZE
96
16
6
6
Mixture of
6, 7, 8
6, 7, 8
108
16