PAC-SYSPOWR1220AT8 Lattice, PAC-SYSPOWR1220AT8 Datasheet - Page 2

• Manufacturer Part Number: PAC-SYSPOWR1220AT8
• Description: MCU, MPU & DSP Development Tools ispPAC Pwr Mgr 1220A T8 Design System
• Manufacturer: Lattice

Specifications of PAC-SYSPOWR1220AT8

• Processor To Be Evaluated: ispPACPOWR1220AT8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
PAC-POWR1220AT8-EV Evaluation Board
Programming Interface
Lattice Semiconductor’s ispDOWNLOAD cable can be used to program the ispPAC-POWR1220AT8 device on the
evaluation board. This cable plugs into a PC-compatible's parallel port connector, and includes active buffer cir-
cuitry inside its DB-25 connector housing. The other end of the ispDOWNLOAD cable terminates in an 8-pin 0.100”
pitch header connector which plugs directly into a mating connector provided on the PAC-POWR1220AT8-EV eval-
uation board (J4).
Power Supply Considerations
The ispPAC-POWR1220AT8 device operates with analog and digital core power supplies of 3.3V, To simplify evalu-
ation work, the evaluation board was designed to operate from a single 4.5V to 5.5V power supply, which may be
brought in through either a pair of banana plugs (J2 and J3), or a standard 5mm power plug (J1 - center tip posi-
tive). The evaluation board provides a linear regulator to provide the appropriate operating voltages for the ispPAC-
POWR1220AT8 device, as well as reverse polarity protection.
Input/Output Connections
Connectors are provided for key functions and test points on this evaluation board, as shown In Figure 2. Power
may be supplied in one of two ways; either through two color coded (RED = +, BLACK = -) banana jacks in the
upper right corner of the board or through a 5mm (center pin +) DC power connector (J1), The JTAG programming
cable is connected to a keyed header (J4) in the upper right corner of the board. Another header (J5) provides
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access to the device’s I
C port. This header is pinned-out, and associated with interface circuitry so that in addition
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to providing a standard I
C bus connection (with on-board 2K pull-ups to 3.3V), it may also be driven by the Lattice
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DL2download cable when the “Power Manager I
C Utility” in PAC-Designer is used.
Access to a subset of the ispPAC-POWR1220AT8 device’s I/O pins is available along the left edge of the assembly,
where a 2x34 block of pads supports the attachment of test probes or a ribbon-cable connector. Pads for accessing
the ATDI and TDISEL signals are provided immediately below the JTAG header (J4). An auxiliary connection for
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OUT5/SMB Alert is provided on a pad below the I
C header (J5).
Figure 2. I/O Connections, Controls and Indicators
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