M1-SYSMGMT-DEV-KIT-FP3 Actel, M1-SYSMGMT-DEV-KIT-FP3 Datasheet - Page 12

• Manufacturer Part Number: M1-SYSMGMT-DEV-KIT-FP3
• Description: MCU, MPU & DSP Development Tools System Management Development Kit
• Manufacturer: Actel

Specifications of M1-SYSMGMT-DEV-KIT-FP3

• Processor To Be Evaluated: AFS1500-FG484
• Interface Type: RS-232, USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Hardware Components
Clocks and Reset
CLK Source
Jumper Settings
Programming
FlashPro3
12
A 50 MHz clock with 50 ppm stability is provided at location U5. This clock is the clock source for the A3P250-FG144
device at U24 (pin F12) and the M1AFS1500-FG484 device at location U23 (pin A3). A user clock is also provided at
location U7. Any 3.3 V clock can be installed in the socket of this location. The user clock feeds only to the
M1AFS1500-FG484 device.
A 32.768 kHz crystal is provided at location Y1 on the board. This is the crystal used to start the internal RTC counter
on the M1AFS1500-FG484 device.
JP25 is a two-pin jumper. By default there is no jumper at this location. In this state, the clock is free running. If the
jumper is placed, it puts the enable pin of the clock to GND and shuts off the clock oscillator.
PUB Signal
The PUB signal of the M1AFS1500-FG484 unit has a 1 MΩ pull to 3.3 V along with a push button SW8 to provide an
active low pulse.
Reset
An active low pin reset is provided by the push button SW6. The reset signal goes to the M1AFS1500-FG484 device at
pin B17 and A3P250 device at pin E2.
Different programming techniques are provided on the System Management Board.
In-system programming is provided to enable programming of all devices on the JTAG boundary scan chain, see
2-1.
Place all jumpers as shown in
JP35
JP13
JP12
Table 2-2 · Jumpers Settings for In-System Programming
Figure 2-1. FlashPro3 In-System Programming Setup
Table 2-2
Jumper
M1AFS
and plug in the FlashPro3 connector on J13 to start programming .
A3P
Setting for In-System Programming
M1 System Management Board User’s Guide
PCI 1
1-2
1-2
1-2
PCI 2
Figure