LCMXO256C-S-EV Lattice, LCMXO256C-S-EV Datasheet - Page 4

• Manufacturer Part Number: LCMXO256C-S-EV
• Description: MCU, MPU & DSP Development Tools Eval Board for MachXO
• Manufacturer: Lattice

Specifications of LCMXO256C-S-EV

• Processor To Be Evaluated: Lattice MachXO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
I/O Voltage
The Lattice MachXO device has two sysIO™ banks; each is capable of supporting multiple I/O standards. Each
sysIO bank has its own I/O supply voltage (V
Refer to the Lattice MachXO Family Data Sheet for additional information about supported I/O standards. This data
sheet can be downloaded from www.latticesemi.com.
The MachXO Starter Evaluation Board allows individual control of each I/O bank capable of supporting V
between 1.2V and 3.3V. The board includes 0 ohm resistors which allow the user to select 3.3V or an adjustable
voltage between 1.25V and 3.3V. During manufacturing, the V
rail (ADJ) is fixed at 2.5V during manufacturing. Table 1 shows the required resistor population to set the appropri-
ate core and I/O voltages.
Table 1. Voltage Jumpers/Settings for V
Device Clocks
The MachXO Starter Evaluation Board provides a variety of ways to supply clock signals to the MachXO device.
These include a 33MHz on-board crystal oscillator, expansion connectors and 0.1” header pins. The on-board
oscillator is connected to MachXO pin 36, which is a dedicated clock input. The oscillator can be enabled/disabled
via pull up (R144) /down (R145), or through pin 44 of the MachXO. Dedicated clock inputs are also available on the
following pins: 38, 85 and 86. These pins are brought out to test points on the PCB, and to the expansion headers.
Device I/O Banks
MachXO I/O banks 0 and 1 are general purpose I/O banks connected to a combination of test pads, switches,
LEDs and two board expansion headers. The switches consist of two user defined push-button switches and an 8-
position DIP switch. Both types of switches are pulled up to the associated V
(when in the up position) and connected to GND when activated (in the down position). LEDs are active (lit) when
the device I/O is low. Table 2 details the I/O banks 0 and 1 connections.
I/Os listed as GPIO (General Purpose I/O) are connected to 0.1” centered plated through hole, with an associated
GND hole and pads for a pull-up or pull-down resistor. The pull-up pads are located on the component side of the
PCB, and the pull-down pads on the solder side. These pads are sized for 0805 components. Each device I/O is
connected to a test point on the PCB. The PCB silkscreen is marked with the corresponding MachXO 100-TQFP
I/O pin.
Table 2. Device I/O Connections
Pin #
1
2
3
4
5
6
7
8
9
VCC_CORE
V
V
1. Default resistor is based on device core I/O voltage, 3.3V for “C” devices, and
CCIO0
CCIO1
1.2V for “E” devices.
Pin Name
PL3C
PL3D
PL2A
PL2B
PL3A
PL3B
PL4A
PL4B
PL5A
CCIO
R157 (default
R148 (default)
R151 (default)
3.3V
CCIO
and VCC_CORE
), which allows each I/O bank to be completely independent.
1
)
4
Expansion Connect
CCIO
R158
R150
R152
ADJ
banks are set to 3.3V. The adjustable voltage
J1-10
J1-11
J1-12
J1-13
J1-5
J1-6
J1-7
J1-8
J1-9
MachXO Starter Evaluation Board
R156(default*)
1.2V
CCIO
N/A
N/A
voltage with 10K Ω resistors
Function/PCB Connect
User’s Guide
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
CCIO