PAC20-EV Lattice, PAC20-EV Datasheet

PAC20-EV

Manufacturer Part Number

PAC20-EV

Description

MCU, MPU & DSP Development Tools ispPAC20 Eval Brd

Manufacturer

Lattice

Datasheet

1.PAC30-EV.pdf (1 pages)

Specifications of PAC20-EV

Processor To Be Evaluated

ispPAC20

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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• QUICKLY CONFIGURE & EVALUATE ispPAC10 DEVICES

• FULLY POPULATED DEVICE EVALUATION BOARD

• TWO ispPAC10-P DIP DEVICE SAMPLES

The Lattice Semiconductor ispPAC10 In-System-Pro-

grammable (ISP™) Analog Circuit allows designers to

build analog circuits, such as gain stages and active

filters, without the use of external feedback resistors or

capacitors. A standard JTAG IEEE 1149.1 interface

allows the user to reconfigure the ispPAC10 while in-

system using on-chip non-volatile E

The ispPAC10 Evaluation Board allows the user to quickly

configure and evaluate the ispPAC10 on a fully as-

sembled PC board. The double-sided board supports a

28-pin DIP package sample (included in the package),

connectors for Input and Output signals, a JTAG pro-

gramming cable interconnect and a prototype array section

for additional circuitry to be added by the user. Each input

and output is accessible to the user through BNC connec-

tors and jumpers. The four JTAG programming signals

have dedicated pins that are tied directly to the

ispDOWNLOAD programming header J5. The board

contains an array of 286 prototype holes that can be used

for experimental evaluation and project interfacing. As an

expansion feature, the programming interface signals,

as well as all analog signals, are connected to dual row

headers, with 34 pads, for ribbon cable or board-to-board

pins. Additional jumpers allow the user to tie any input to

the internal VREF

board contains a momentary push-button switch that can

be used to initiate calibration. The calibration adjusts

output offset and nulls the offset errors to a fraction of a

millivolt. Decoupling and bypass capacitors are located

on the board near the ispPAC10 device. Two banana

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

pac10ev_01

Features

Description

— VS and Ground Connectors

— Decoupling and Bypass Capacitors

— BNCs for Input and Output Pins

— Jumpers Connect Inputs and Outputs to the BNCs

— 8-Pin Header Connector JTAG Programming

— Interfaces with Lattice’s ispDOWNLOAD

— User Prototype Array for Custom Circuits

Through PC Parallel Port DB-25 Connector

OUT

common reference circuit. The

CMOS

technology.

Cable

For Configuration and Evaluation of ispPAC10 Devices

Figure 1. ispPAC10 Evaluation Board EV-2A

plug receptacles are available for Vs and GND connec-

tions. A third pin is used when the optional CMV

reference voltage is externally supplied.

Toll Free Hotline:

International:

E-mail:

Internet:

Ordering Information

Technical Support Assistance

Ordering Number

ispPAC 10 -EV-2A

PAC10-EV

Evaluation Board

attice

Semiconductor

.1uF

ispPAC10

1-800-LATTICE (Domestic)

1-408-826-6002

ispPACs@latticesemi.com

http://www.latticesemi.com

ispPAC10 Evaluation Board

ispPAC 10

Description

September 1999

1 inch

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