Si4720-A-EVB Silicon Laboratories Inc, Si4720-A-EVB Datasheet - Page 30

• Manufacturer Part Number: Si4720-A-EVB
• Description: WiFi / 802.11 Modules & Development Tools Si4720 Eval Board Use Si4721-A-EVB.
• Manufacturer: Silicon Laboratories Inc

Specifications of Si4720-A-EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si4720/21-B20
programmed with the value 6750, the Transmit Pilot
Deviation with 750, and the Transmit RDS Deviation
with 200, generating peak audio frequency deviations of
67.5 kHz, peak pilot deviations of 7.5 kHz, and peak
RDS deviations of 2.0 kHz for a total peak frequency
deviation of 77 kHz. The total peak transmit frequency
deviation of the Si4720/21 can range from 0 to 100 kHz
and is equal to the arithmetic sum of the Transmit
Audio, Pilot, and RDS deviations. Users must comply
with local regulations on radio frequency transmissions.
Each of the individual deviations (transmit audio, pilot,
and RDS) can be independently programmed; however,
the total peak frequency deviation cannot exceed
100 kHz.
The Si4720/21 provides an overmodulation indicator to
allow the user to dynamically set the maximum
deviation level. If the instantaneous frequency exceeds
the
TX_AUDIO_DEVIATION property, the SQINT interrupt
bit (and optional interrupt) will be set.
5.16. Transmitter Digital Audio Interface
The digital audio interface operates in slave mode and
supports 3 different audio data formats:
1. I
2. Left-Justified
3. DSP Mode
5.16.1. Audio Data Formats
In I
edge of DCLK following each DFS transition. The
remaining bits of the word are sent in order, down to the
LSB. The Left Channel is transferred first when the DFS
is low, and the Right Channel is transferred when the
DFS is high.
30
(IMODE = 0000)
(IFALL = 1)
(IFALL = 0)
2
2
I2S
S mode, the MSB is captured on the second rising
S
deviation
DIN/DOUT
INVERTED
DCLK
DCLK
DFS
level
1 DCLK
MSB
1
specified
2
Figure 21. I
3
LEFT CHANNEL
by
n-2
2
S Digital Audio Format
n-1
the
Rev. 1.0
LSB
n
In Left-Justified mode, the MSB is captured on the first
rising edge of DCLK following each DFS transition. The
remaining bits of the word are sent in order, down to the
LSB. The Left Channel is transferred first when the DFS
is high, and the Right Channel is transferred when the
DFS is low.
In DSP mode, the DFS becomes a pulse with a width of
1 DCLK period. The Left Channel is transferred first,
followed right away by the Right Channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
In all audio formats, depending on the word size, DCLK
frequency and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
5.16.2. Audio Sample Rates
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs and ADCs on
the audio baseband processor. The sampling rate is
selected using the DIGITAL_INPUT_SAMPLE_RATE
property.
The device supports DCLK frequencies above 1 MHz.
After powerup the DIGITAL_INPUT_SAMPLE_RATE
property defaults to 0 (disabled). After DCLK is
supplied,
property should be set to the desired audio sample rate
such
DIGITAL_INPUT_SAMPLE_RATE property must be set
to 0 before DCLK is removed or the DCLK frequency
drops below 1 MHz. A device reset is required if this
requirement is not followed.
as
1 DCLK
the
32,
MSB
1
2
40,
DIGITAL_INPUT_SAMPLE_RATE
3
RIGHT CHANNEL
44.1,
n-2
or
n-1
48 kHz.
LSB
n
The