CY7C1049DV33-10ZSXIT Cypress Semiconductor Corp, CY7C1049DV33-10ZSXIT Datasheet - Page 6

• Manufacturer Part Number: CY7C1049DV33-10ZSXIT
• Description: CY7C1049DV33-10ZSXIT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1049DV33-10ZSXIT

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 4M (512K x 8)
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSOP II
• Memory Configuration: 512K X 8
• Access Time: 10ns
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC Switching Characteristics
Over the Operating Range
Document Number: 38-05475 Rev. *G
Notes
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I
8. t
9. At any temperature and voltage condition, t
10. t
11. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals
12. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of t
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
Parameter
and 30 pF load capacitance.
can terminate the write. The input data set up and hold timing must be referred to the leading edge of the signal that terminates the write.
POWER
HZOE
[8]
, t
HZCE
gives the minimum amount of time that the power supply must be at stable, typical V
, and t
[11, 12]
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power up
CE HIGH to Power down
Write Cycle Time
CE LOW to Write End
Address Set up to Write End
Address Hold from Write End
Address Set up to Write Start
WE Pulse Width
Data Set up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
CC
HZWE
(typical) to the first access
are specified with a load capacitance of 5 pF as in part (c) of
[7]
[9]
[9]
[9, 10]
[9]
[9, 10]
[9, 10]
HZCE
Description
is less than t
LZCE
, t
HZOE
is less than t
Figure 1 on page
LZOE
, and t
HZWE
CC
HZWE
5. Transition is measured when the outputs enter a high impedance state.
values until the first memory access is performed.
Min
100
-10 (Industrial)
10
10
is less than t
–
3
–
–
0
–
3
–
0
–
7
7
0
0
7
5
0
3
–
and t
SD
.
LZWE
Max
10
10
10
for any given device.
–
–
–
5
–
5
–
5
–
–
–
–
–
–
–
–
–
–
5
-12 (Automotive)
Min
100
12
12
CY7C1049DV33
–
3
–
–
0
–
3
–
0
–
8
8
0
0
8
6
0
3
–
Max
12
12
12
–
–
–
6
–
6
–
6
–
–
–
–
–
–
–
–
–
–
6
Page 6 of 14
Unit
OL
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/I
OH
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