XC3S1500-4FG456C Xilinx Inc, XC3S1500-4FG456C Datasheet
XC3S1500-4FG456C
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XC3S1500-4FG456C Summary of contents
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R DS099 May 25, 2007 This document includes all four modules of the Spartan™-3 FPGA data sheet. Module 1: Introduction and Ordering Information DS099-1 (v2.2) May 25, 2007 • Introduction • Features • Architectural Overview • Array Sizes and Resources ...
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R DS099 May 25, 2007 Product Specification ...
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... XC3S200 200K 4,320 24 2 XC3S400 400K 8,064 32 2 XC3S1000 1M 17,280 48 XC3S1500 1.5M 29,952 64 XC3S2000 2M 46,080 80 XC3S4000 4M 62,208 96 XC3S5000 5M 74,880 104 Notes: 1. Logic Cell = 4-input Look-Up Table (LUT) plus a ‘D’ flip-flop. "Equivalent Logic Cells" equals "Total CLBs" Logic Cells/CLB x 1.125 effectiveness. ...
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Spartan-3 FPGA Family: Introduction and Ordering Information Architectural Overview The Spartan-3 family architecture consists of five funda- mental programmable functional elements: • Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to implement logic and storage elements that can be ...
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R Configuration Spartan-3 FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configura- tion latches (CCLs) that collectively control all functional elements and routing resources. Before powering on the FPGA, configuration data is stored externally in a ...
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... CPG132 Device User Diff User Diff User XC3S50 XC3S200 XC3S400 - - - - XC3S1000 - - - - XC3S1500 - - - - XC3S2000 - - - - XC3S4000 - - - - XC3S5000 - - - - Notes: 1. All device options listed in a given package column are pin-compatible. 2. User = Single-ended user I/O pins. Diff = Differential I/O pairs Available User I/Os and Differential (Diff) I/O Pairs by Package Type ...
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R Package Marking Figure 2 shows the top marking for Spartan-3 FPGAs in the quad-flat packages. Figure 3 shows the top marking for Spartan-3 FPGAs in BGA packages except the 132-ball chip-scale package (CP132 and CPG132). The markings for the ...
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... Example: Device Type Speed Grade Package Type Device Speed Grade XC3S50 -4 Standard Performance 1 XC3S200 -5 High Performance XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Notes: 1. The -5 speed grade is exclusively available in the Commercial temperature range XC3S50 -4 PQ 208 C Temperature Range Commercial ( Industrial (T Number of Pins : " ...
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R Revision History Date Version No. 04/11/03 1.0 Initial Xilinx release. 04/24/03 1.1 Updated block RAM, DCM, and multiplier counts for the XC3S50. 12/24/03 1.2 Added the FG320 package. 07/13/04 1.3 Added information on Pb-free packaging options. 01/17/05 1.4 Referenced ...
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Spartan-3 FPGA Family: Introduction and Ordering Information 10 10 www.xilinx.com R DS099-1 (v2.2) May 25, 2007 Product Specification ...
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R DS099-2 (v2.2) May 25, 2007 New Spartan-3 Generation Design Documentation Available ™ The functionality of the Spartan -3 FPGA family is now described and updated in the following documents. The topics covered in each guide are listed below. • ...
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Spartan-3 FPGA Family: Functional Description IOBs For additional information, refer to the “Using I/O Resources” chapter in UG331. IOB Overview The Input/Output Block (IOB) provides a programmable, bidirectional interface between an I/O pin and the FPGA’s internal logic. A simplified ...
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TCE OTCLK1 CK SR OCE OTCLK2 IQ1 D CE ICLK1 CK SR ICE IQ2 D CE ICLK2 CK SR ...
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Spartan-3 FPGA Family: Functional Description According to Figure 5, the clock line OTCLK1 connects the CK inputs of the upper registers on the output and three-state paths. Similarly, OTCLK2 connects the CK inputs for the lower registers on the output ...
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R DCM 180˚ 0˚ CLK1 DDR MUX D2 Q2 CLK2 Figure 6: Clocking the DDR Register Pull-Up and Pull-Down Resistors The optional pull-up and pull-down resistors are intended to establish High and Low levels, respectively, at unused I/Os. ...
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Spartan-3 FPGA Family: Functional Description Together with placing the appropriate I/O symbol, two exter- nally applied voltage levels, V CCO desired signal standard. The V CCO the output driver. The voltage on these lines determines the output voltage swing for ...
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R match the characteristic impedance of the transmission line. This adjustment process compensates for differences in I/O impedance that can result from normal variation in the ambient temperature, the supply voltage and the manufac- turing process. When the output driver ...
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Spartan-3 FPGA Family: Functional Description Table 9: DCI I/O Standards (Continued) Category of Signal Signal Standard Standard (IOSTANDARD) Differential Low-Voltage LVDS_25_DCI Differential LVDSEXT_25_DCI Signalling Notes: 1. DCI signal standards are not supported in Bank 5 of any Spartan-3 FPGA packaged ...
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R Table 10: DCI Terminations Termination Controlled impedance output driver Controlled output driver with half impedance Single resistor Split resistors Split resistors with output driver impedance fixed to 25Ω Notes: 1. The value equivalent to the characteristic ...
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Spartan-3 FPGA Family: Functional Description The DCI feature operates independently for each of the device’s eight banks. Each bank has an ‘N’ reference pin (VRN) and a ‘P’ reference pin, (VRP), to calibrate driver and termination resistance. Only when using ...
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R Xilinx development software checks for this. Tables 7, 8, and 9 describe how different standards use the V supply. 4. Only one of the following standards is allowed on outputs per bank: LVDS, LDT, LVDS_EXT, or RSDS ...
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Spartan-3 FPGA Family: Functional Description . Switch Matrix SHIFTOUT SHIFTIN CLB Overview For more details on the CLBs, refer to the “Using Config- urable Logic Blocks” chapter in UG331. The Configurable Logic Blocks (CLBs) constitute the main logic resource for ...
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R Notes: 1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown. 2. The index i can depending on the slice. In this position, the ...
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Spartan-3 FPGA Family: Functional Description The carry chain, together with various dedicated arithmetic logic gates, support fast and efficient implementations of math operations. The carry chain enters the slice as CIN and exits as COUT. Five multiplexers control the chain: ...
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... Addressable Device of RAM Blocks Locations (bits) XC3S50 4 XC3S200 12 221,184 XC3S400 16 294,912 XC3S1000 24 442,368 XC3S1500 32 589,824 XC3S2000 40 737,280 XC3S4000 96 1,769,472 XC3S5000 104 1,916,928 DS099-2 (v2.2) May 25, 2007 Product Specification Block RAM and multipliers have interconnects between them that permit simultaneous operation; however, since ...
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Spartan-3 FPGA Family: Functional Description RAMB16_Sw WEA ENA SSRA CLKA ADDRA[r –1:0] A DIA[w –1:0] A DIPA[3:0] WEB ENB SSRB CLKB ADDRB[r –1:0] B DIB[w –1:0] B DIPB[3:0] (a) Dual-Port Notes and w are integers representing the total ...
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R Table 12: Block RAM Port Signals (Continued) Port A Port B Signal Signal Signal Description Name Data Output DOA Bus Parity Data DOPA Output(s) Write Enable WEA Clock Enable ENA Set/Reset SSRA Clock CLKA Port Aspect Ratios On a ...
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Spartan-3 FPGA Family: Functional Description Block RAM automatically performs a bus-matching func- tion. When data are written to a port with a narrow bus, then read from a port with a wide bus, the latter port will effec- tively combine ...
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R CLK WE DI ADDR DO 0000 EN DISABLED Figure 13: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected Choosing the READ_FIRST attribute, data already stored in the addressed location pass to the DO outputs before that location is ...
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Spartan-3 FPGA Family: Functional Description CLK WE DI ADDR DO 0000 EN DISABLED Figure 15: Waveforms of Block RAM Data Operations with NO_CHANGE Selected Dedicated Multipliers All Spartan-3 devices provide embedded multipliers that accept two 18-bit words as inputs to ...
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R Table 14: Embedded Multiplier Primitives Descriptions Signal Name Direction A[17:0] Input Apply one 18-bit multiplicand to these inputs. The MULT18X18S primitive requires a setup time before the enabled rising edge of CLK. B[17:0] Input Apply the other 18-bit multiplicand ...
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Spartan-3 FPGA Family: Functional Description PSINCDEC PSEN PSCLK CLKIN CLKFB RST Figure 17: DCM Functional Blocks and Associated Signals The DCM has four functional Delay-Locked Loop (DLL), the Digital Frequency Synthe- sizer (DFS), the Phase Shifter (PS), and the Status ...
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R The DLL component has two clock inputs, CLKIN and CLKFB, as well as seven clock outputs, CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as described in Table 15. The clock outputs drive simulta- neously; however, the High Frequency ...
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Spartan-3 FPGA Family: Functional Description Table 16: DLL Attributes Attribute CLK_FEEDBACK DLL_FREQUENCY_MODE CLKIN_DIVIDE_BY_2 CLKDV_DIVIDE DUTY_CYCLE_CORRECTION DLL Clock Input Connections An external clock source enters the FPGA using a Global Clock Input Buffer (IBUFG), which directly accesses the glo- bal clock ...
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R FPGA CLK90 BUFG CLK180 CLKIN CLK270 CLKDV DCM CLK2X CLK2X180 CLKFB CLK0 CLK0 (a) On-Chip with CLK0 Feedback FPGA CLK90 IBUFG CLK180 CLKIN CLK270 CLKDV DCM CLK2X CLK2X180 CLKFB CLK0 IBUFG CLK0 (c) Off-Chip with CLK0 Feedback Notes: 1. ...
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Spartan-3 FPGA Family: Functional Description Their relative timing in the Low Frequency Mode is shown in Figure 20. The CLK90, CLK180 and CLK270 outputs are not available when operating in the High Frequency mode. (See the description of the DLL_FREQUENCY_MODE ...
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R Digital Frequency Synthesizer (DFS) The DFS component generates clock signals the frequency of which is a product of the clock frequency at the CLKIN input and a ratio of two user-determined integers. Because of the wide range of possible ...
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Spartan-3 FPGA Family: Functional Description DFS Clock Output Connections There are two basic cases that determine how to connect the DFS clock outputs: on-chip and off-chip, which are illus- trated in Figure 19a and Figure 19c, respectively. This is similar ...
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R Table 19: PS Attributes Attribute CLKOUT_PHASE_SHIFT Disables PS component or chooses between Fixed Phase and Variable Phase modes. PHASE_SHIFT Determines size and direction of initial fine phase shift. Notes: 1. The practical range of values will be less when ...
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Spartan-3 FPGA Family: Functional Description Table 20: Signals for Variable Phase Mode Signal Direction (1) PSEN Input Enables PSCLK for variable phase adjustment. (1) PSCLK Input Clock to synchronize phase shift adjustment. (1) PSINCDEC Input Chooses between increment and decrement ...
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R Table 22: DCM STATUS Bus Bit Name 0 Phase Shift A value of 1 indicates a phase shift overflow when one of two conditions occurs: Overflow • • 1 CLKIN Input A value of 1 indicates that the CLKIN ...
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Spartan-3 FPGA Family: Functional Description Table 24: BUFGMUX Select Mechanism S Input 0 1 The two clock inputs can be asynchronous with regard to each other, and the S input can change at any time, except for a short setup ...
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R 4 DCM 4 DCM DS099-2 (v2.2) May 25, 2007 Product Specification GCLK6 GCLK4 GCLK5 GCLK7 4 4 BUFGMUX 4 • • • Horizontal Spine • • • BUFGMUX 4 GCLK3 GCLK1 GCLK2 GCLK0 Figure 22: ...
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Spartan-3 FPGA Family: Functional Description Interconnect Interconnect (or routing) passes signals among the various functional elements of Spartan-3 devices. There are four kinds of interconnect: Long lines, Hex lines, Double lines, and Direct lines. Long lines connect to one out ...
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... M0-M2. These pins are powered by the V Table 26: Spartan-3 Configuration Data Device XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 The Dual-Purpose configuration pins comprise INIT_B, DOUT, BUSY, RDWR_B, CS_B, and DIN/D0-D7. Each of these pins, according to its bank placement, uses the V lines for either Bank 4 (VCCO_4 on most packages, VCCO_BOTTOM on TQ144 and CP132 packages) or Bank www ...
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Spartan-3 FPGA Family: Functional Description 5 (VCCO_5). All the signals used in the serial configuration modes rely on VCCO_4 power. Signals used in the parallel configuration modes and Readback require from VCCO_5 as well as from VCCO_4. Both the Dedicated ...
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R 3.3V: XCF0xS 1.8V: XCFxxP V CCO V CCINT Platform Flash PROM XCF0xS or XCFxxP OE/RESET GND Notes: 1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for ...
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Spartan-3 FPGA Family: Functional Description when operating in the User mode. This is accomplished by setting the Persist option to Yes. Multiple FPGAs can be configured using the Slave Parallel mode and can be made to start-up simultaneously. Figure 25 ...
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R Notes: 1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for the last FPGA to be configured in the chain shown above (or for the single FPGA ...
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Spartan-3 FPGA Family: Functional Description Figure 27: Configuration Flow Diagram for the Serial and Parallel Modes 50 54 Set PROG_B Low Power-On after Power-On V >1V CCINT No and V > 2V CCAUX and V Bank 4 > 1V CCO ...
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R and V No (JTAG port becomes No Figure 28: Boundary-Scan Configuration Flow Diagram DS099-2 (v2.2) May 25, 2007 Product Specification Set PROG_B Low Power-On after Power-On V >1V CCINT and V > CCAUX Bank 4 > 1V ...
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Spartan-3 FPGA Family: Functional Description Configuration is automatically initiated after power-on unless it is delayed by the user. INIT_B is an open-drain line that the FPGA holds Low during the clearing of the configu- ration memory. Extending the time that ...
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R threshold levels (see Table 28, page supplies reach their respective threshold, the POR reset is released and the FPGA begins its configuration process. Because the three supply inputs must be valid to release the POR reset and can be ...
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Spartan-3 FPGA Family: Functional Description Revision History Date Version No. 04/11/03 1.0 Initial Xilinx release 05/19/03 1.1 Added Block RAM column, DCMs, and multipliers to XC3S50 descriptions. 07/11/03 1.2 Explained the configuration port Persist option in Updated for the XC3S50 ...
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R DS099-3 (v2.2) May 25, 2007 DC Electrical Characteristics In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as follows: Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 27: Absolute Maximum Ratings (Continued) Symbol Description V Electrostatic Discharge Voltage pins relative ESD to GND T Junction temperature J T Soldering temperature SOL T Storage temperature STG Notes: 1. Stresses beyond ...
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... Spartan-3 FPGA Family: DC and Switching Characteristics (2) Top Marking Device Mask revisions ‘A’ XC3S50 through ‘D’ XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Mask revisions ‘E’ or All later Devices with ‘FQ’ All fabrication/process code not specifically ordered with SCD0961 Devices with ‘ ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 31: General Recommended Operating Conditions Symbol T Junction temperature J V Internal supply voltage CCINT (1) V Output driver supply voltage CCO V Auxiliary supply voltage CCAUX ΔV (2) Voltage variance on ...
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R Table 32: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (Continued) Symbol Description (3) R Equivalent resistance of pull-down resistor PD at User I/O, Dual-Purpose, and Dedicated pins, driven from I RPD R Value of external reference ...
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... XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 supply current XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Table 31. Quiescent supply current is measured with all I/O drivers of 25° 1.26V 3.45V, and V = 2.625V. The FPGA is programmed with a "blank" CCO CCAUX provides quick, approximate, typical estimates, and does not ...
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R Table 34: Recommended Operating Conditions for User I/Os Using Single-Ended Standards Signal Standard (IOSTANDARD) Min (V) Nom (V) (3) GTL - GTL_DCI - (3) GTLP - GTLP_DCI - HSLVDCI_15 1.4 HSLVDCI_18 1.7 HSLVDCI_25 2.3 HSLVDCI_33 3.0 HSTL_I, HSTL_I_DCI 1.4 ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 35: DC Characteristics of User I/Os Using Single-Ended Standards Signal Standard (IOSTANDARD) and Current Drive Attribute (mA) GTL GTL_DCI GTLP GTLP_DCI HSLVDCI_15 HSLVDCI_18 HSLVDCI_25 HSLVDCI_33 HSTL_I HSTL_I_DCI HSTL_III HSTL_III_DCI HSTL_I_18 HSTL_I_DCI_18 HSTL_II_18 ...
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R Table 35: DC Characteristics of User I/Os Using Single-Ended Standards (Continued) Signal Standard (IOSTANDARD) and Current Drive Attribute (mA) (4) LVCMOS33 LVDCI_33, LVDCI_DV2_33 (4) LVTTL ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Internal Logic V V GND level Table 36: Recommended Operating Conditions for User I/Os Using Differential Signal Standards V CCO Signal Standard Min Nom (IOSTANDARD) (V) (V) LDT_25 (ULVDS_25) 2.375 2.50 LVDS_25, 2.375 ...
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R Internal Logic V OUTN V OUTP GND level Table 37: DC Characteristics of User I/Os Using Differential Signal Standards (1) Mask Signal Standard Revision LDT_25 (ULVDS_25) All LVDS_25 All ‘E’ (6) BLVDS_25 All LVDSEXT_25 All ‘E’ (6) LVPECL_25 All ...
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... Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated to the simulation netlist. Table 38: Spartan-3 Speed Grade Designations (ISE v8.2i or later) Device Advance XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 www.xilinx.com R more precise, and Preliminary Production – ...
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... XC3S1500 XC3S2000 XC3S4000 XC3S5000 (2) LVCMOS25 , XC3S50 12mA output drive, XC3S200 Fast slew rate, XC3S400 without DCM XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Table 47 Table 43. If the latter is true, add the appropriate Output adjustment from www.xilinx.com Speed Grade -MIN -5 -4 Min Max Max ...
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... XC3S200 (4) with DCM XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 (3) LVCMOS25 , XC3S50 IOBDELAY = IFD, XC3S200 without DCM XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Table 47 and are based on the operating conditions set www.xilinx.com Speed Grade -5 -4 Min Min Units 2.37 2.71 ns 2.13 2. ...
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... XC3S5000 -0.68 -0.68 XC3S50 -2.74 -2.74 XC3S200 -3.00 -3.00 XC3S400 -2.90 -2.90 XC3S1000 -3.24 -3.24 XC3S1500 -3.55 -3.55 XC3S2000 -4.57 -4.57 XC3S4000 -4.96 -4.96 XC3S5000 -5.09 -5.09 All 0.66 0.76 and are based on the operating conditions set forth in Units ...
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... LVCMOS25 , XC3S50 IOBDELAY = NONE XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 (2) LVCMOS25 , XC3S50 IOBDELAY = IFD XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Table 47 and are based on the operating conditions set Table 43. www.xilinx.com R Speed Grade -5 -4 Max Max Units 2.01 2.31 ns 1.50 1 ...
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R Table 43: Input Timing Adjustments for IOB Add the Adjustment Below Convert Input Time from LVCMOS25 to the Speed Grade Following Signal Standard (IOSTANDARD) -5 Single-Ended Standards GTL, GTL_DCI 0.44 GTLP, GTLP_DCI 0.36 HSLVDCI_15 0.51 HSLVDCI_18 0.29 HSLVDCI_25 0.51 ...
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... XC3S5000 XC3S200 XC3S400 XC3S50 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 (2) LVCMOS25 , 12mA XC3S200 output drive, Fast slew XC3S400 rate XC3S50 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 All Table 47 and are based on the operating conditions set Table 46. www.xilinx.com R Speed Grade - Min Max Max Units ...
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... XC3S400 slew rate XC3S50 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 LVCMOS25, 12mA All output drive, Fast slew rate XC3S200 XC3S400 XC3S50 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Table 47 and are based on the operating conditions set Table 46. www.xilinx.com Speed Grade - Min Max Max Units ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 46: Output Timing Adjustments for IOB Convert Output Time from Adjustment Below LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) -MIN Single-Ended Standards GTL 0 GTL_DCI ...
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R Table 46: Output Timing Adjustments for IOB (Continued) Convert Output Time from Adjustment Below LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) -MIN LVCMOS33 Slow ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Timing Measurement Methodology When measuring timing parameters at the programmable I/Os, different signal standards call for different test condi- tions. Table 47 presents the conditions to use for each stan- dard. The method ...
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R Table 47: Test Methods for Timing Measurement at I/Os (Continued) Signal Standard (IOSTANDARD) V (V) REF LVCMOS18 - LVDCI_18 LVDCI_DV2_18 LVCMOS25 - LVDCI_25 LVDCI_DV2_25 LVCMOS33 - LVDCI_33 LVDCI_DV2_33 LVTTL - PCI33_3 Rising - Falling SSTL18_I 0.9 SSTL18_I_DCI SSTL18_II 0.9 ...
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Spartan-3 FPGA Family: DC and Switching Characteristics The capacitive load ( connected between the output L and GND. The Output timing for all standards, as published in the speed files and the data sheet, is always based on ...
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... CCO (1) Device VQ100 CP132 XC3S50 1 1.5 XC3S200 1 - XC3S400 - - XC3S1000 - - XC3S1500 - - XC3S2000 - - XC3S4000 - - XC3S5000 - - Notes: 1. The V lines for the pair of banks on each side of the CP132 and TQ144 packages are internally tied together. Each CCO pair of interconnected banks shares three V 2. The information in this table also applies to Pb-free packages. ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 49: Recommended Number of Simultaneously Switching Outputs per V -GND Pair CCO Signal Standard VQ TQ (IOSTANDARD) 100 144 Single-Ended Standards GTL 0 0 GTL_DCI 0 0 GTLP 0 0 GTLP_DCI 0 ...
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R Table 49: Recommended Number of Simultaneously Switching Outputs per V -GND Pair (Continued) CCO Signal Standard VQ TQ (IOSTANDARD) 100 144 LVCMOS33 Slow ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Internal Logic Timing Table 50: CLB Timing Symbol Clock-to-Output Times T When reading from the FFX (FFY) Flip-Flop, CKO the time from the active transition at the CLK input to data appearing at ...
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R Table 51: CLB Distributed RAM Switching Characteristics Symbol Clock-to-Output Times T Time from the active edge at the CLK input to data SHCKO appearing on the distributed RAM output Setup Times T Setup time of data at the BX ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 53: Synchronous Multiplier Timing Symbol Description Clock-to-Output Times T When reading from the MULTCK Multiplier, the time from the active transition at the C clock input to data appearing ...
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R Table 55: Block RAM Timing Symbol Description Clock-to-Output Times T When reading from the Block BCKO RAM, the time from the active transition at the CLK input to data appearing at the DOUT output Setup Times T Time from ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Digital Clock Manager (DCM) Timing For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Fre- quency Synthesizer (DFS), and the Phase Shifter (PS). Aspects of DLL ...
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... XC3S50 - 150 - 150 ± ± XC3S200 - 150 - 150 ± ± XC3S400 - 250 - 250 ± ± XC3S1000 - 400 - 400 ± ± XC3S1500 - 400 - 400 ± ± XC3S2000 - 400 - 400 ± ± XC3S4000 - 400 - 400 ± ± XC3S5000 - 400 - 400 ± ± All ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 58: Switching Characteristics for the DLL (Continued) Symbol Lock Time LOCK_DLL When using the DLL alone: The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED ...
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... Note 3 Note 3 Note 3 Note 3 ± ± XC3S50 - 100 - ± ± XC3S200 - 100 - ± ± XC3S400 - 250 - ± ± XC3S1000 - 400 - ± ± XC3S1500 - 400 - ± ± XC3S2000 - 400 - ± ± XC3S4000 - 400 - ± ± XC3S5000 - 400 - ± ± All - 300 - All - 10 ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Phase Shifter (PS) Phase Shifter operation is only supported if the DLL is in the Low frequency mode, see Table 61: Recommended Operating Conditions for the PS in Variable Phase Mode Symbol Description ...
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R Miscellaneous DCM Timing Table 63: Miscellaneous DCM Timing Symbol DCM_INPUT_CLOCK_STOP Maximum duration that the CLKIN and CLKFB signals can be stopped DCM_RST_PW_MIN Minimum duration of a RST pulse width (3) DCM_RST_PW_MAX Maximum duration of a RST pulse width (4) ...
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... Max XC3S50 - 5 XC3S200 - 5 XC3S400 - 5 XC3S1000 - 5 XC3S1500 - 7 XC3S2000 - 7 XC3S4000 - 7 XC3S5000 - 7 All 0.3 - XC3S50 - 2 XC3S200 - 2 XC3S400 - 2 XC3S1000 - 2 XC3S1500 - 3 XC3S2000 - 3 XC3S4000 - 3 XC3S5000 - 3 All 250 - All 0.5 4.0 Table 31. This means power must be applied to all DS099-3 (v2.2) May 25, 2007 Product Specification R 1.2V 2.5V Units μ ...
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R PROG_B (Input) INIT_B (Open-Drain) CCLK (Input/Output) DIN (Input) DOUT (Output) Figure 35: Waveforms for Master and Slave Serial Configuration Table 65: Timing for the Master and Slave Serial Configuration Modes Symbol Clock-to-Output Times T The time from the falling ...
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Spartan-3 FPGA Family: DC and Switching Characteristics PROG_B (Input) INIT_B (Open-Drain) CS_B (Input) RDWR_B (Input) CCLK (Input/Output (Inputs) High-Z BUSY (Output) Notes: 1. Switching RDWR_B High or Low while holding CS_B Low asynchronously aborts configuration. Figure 36: ...
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R Table 66: Timing for the Master and Slave Parallel Configuration Modes (Continued) Symbol Hold Times T The time from the rising transition at the CCLK pin to the point SMCCD when data is last held at the D0-D7 pins ...
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Spartan-3 FPGA Family: DC and Switching Characteristics TCK (Input) TMS (Input) TDI (Input) TDO (Output) Table 67: Timing for the JTAG Test Access Port Symbol Clock-to-Output Times T The time from the falling transition on the TCK pin to data ...
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R Revision History Date Version No. 04/11/03 1.0 Initial Xilinx release. 07/11/03 1.1 Extended Absolute Maximum Rating for junction temperature in supply current 02/06/04 1.2 Revised V (Table 32), and differential output voltage levels numbers LVPECL standards 03/04/04 1.3 Added ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Date Version No. 04/03/06 2.0 Upgraded Module 3, removing Preliminary status. Moved XC3S5000 to Production status in Finalized I/O timing on XC3S5000 for v1.38 speed files. Added minimum timing values for various logic ...
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R DS099-4 (v2.2) May 25, 2007 Introduction This data sheet module describes the various pins on a Spartan™-3 FPGA and how they connect to the supported component packages. • The Pin Types section categorizes all of the FPGA pins by ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 68: Types of Pins on Spartan-3 FPGAs (Continued) Type/ Color Code VREF Dual-purpose pin that is either a user-I/O pin or, along with all other VREF pins in the same bank, provides a reference ...
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R Table 69: Spartan-3 Pin Definitions Pin Name Direction I/O: General-purpose I/O pins I/O User-defined as input, output, bidirectional, three-state output, open-drain output, open-source output I/O_Lxxy_# User-defined as input, output, bidirectional, three-state output, open-drain output, open-source output DUAL: Dual-purpose configuration ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 69: Spartan-3 Pin Definitions (Continued) Pin Name Direction IO_Lxxy_#/INIT_B Bidirectional (open-drain) during configuration User I/O after configuration DCI: Digitally Controlled Impedance reference resistor input pins IO_Lxxy_#/VRN_# or Input when using DCI IO/VRN_# Otherwise, same ...
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R Table 69: Spartan-3 Pin Definitions (Continued) Pin Name Direction DONE Bidirectional with open-drain or totem-pole Output M0, M1, M2 Input HSWAP_EN Input JTAG: JTAG interface pins (pull-up resistor to VCCAUX always active during configuration, regardless of HSWAP_EN pin) TCK ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 69: Spartan-3 Pin Definitions (Continued) Pin Name Direction VCCAUX: Auxiliary voltage supply pins VCCAUX Supply VCCINT: Internal core voltage supply pins VCCINT Supply GND: Ground supply pins GND Supply N.C.: Unconnected package pins N.C. ...
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R Bank 0 Bank 1 Bank 5 Bank 4 DUAL Type: Dual-Purpose Configuration and I/O Pins These pins serve dual purposes. The user-I/O pins are tem- porarily borrowed during the configuration process to load configuration data into the FPGA. After ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 70: Dual-Purpose Pins Used in Master or Slave Serial Mode Pin Name Direction DIN Input Serial Data Input: During the Master or Slave Serial configuration modes, DIN is the serial configuration data input, and ...
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R Assert Low both the chip-select pin, CS_B, and the read/write control pin, RDWR_B, to write the configuration data byte presented on the D0-D7 pins to the FPGA on a rising-edge of the configuration clock, CCLK. The order of CS_B ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 71: Dual-Purpose Configuration Pins for Parallel (SelectMAP) Configuration Modes (Continued) Pin Name Direction RDWR_B Input Read/Write Control for Parallel Mode Configuration: In Master and Slave Parallel modes, assert this pin Low together with CS_B ...
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R One of eight I/O Banks User I/O User I/O (a) No termination DCI: User I/O or Digitally Controlled Impedance Resistor Reference Input These pins are individual user-I/O pins unless one of the I/O standards used in the bank requires ...
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Spartan-3 FPGA Family: Pinout Descriptions CCLK: Configuration Clock The configuration clock signal on this pin synchronizes the reading or writing of configuration data. The CCLK pin is an input-only pin for the Slave Serial and Slave Parallel config- uration modes. ...
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R Table 73: DonePin and DriveDone Bitstream Option Interaction Single- or Multi- DonePin DriveDone FPGA Design Pullnone No Single Pullnone No Pullnone Yes Single Pullnone Yes Pullup No Single Pullup No Pullup Yes Single Pullup Yes M2, M1, M0: Configuration ...
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... Table 77: Spartan-3 JTAG IDCODE Register Values (hexadecimal) Figure 41 and Part Number XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 49. XC3S2000 XC3S4000 XC3S5000 TDO Using JTAG Port After Configuration The JTAG port is always active and available before, during, and after FPGA configuration. Add the BSCAN_SPARTAN3 primitive to the design to create user-defined JTAG instruc- tions and JTAG chains to communicate with internal logic ...
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R The TDO output can directly drive a 3.3V input but with reduced noise immunity. See 3.3V-Tolerant Configuration Interface, page 46 or XAPP453: The 3.3V Configuration of for additional details. Spartan-3 FPGAs The following interface precautions are recommended when connecting ...
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Spartan-3 FPGA Family: Pinout Descriptions VCCAUX Type: Voltage Supply for Auxiliary Logic The VCCAUX pins supply power to various auxiliary cir- cuits, such as to the Digital Clock Managers (DCMs), the JTAG pins, and to the dedicated configuration pins (CON- ...
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R Table 78: Pin Behavior After Power-Up, During Configuration (Continued) Serial Modes Master Pin Name <0:0:0> IO_Lxxy_#/ D5 IO_Lxxy_#/ D6 IO_Lxxy_#/ D7 IO_Lxxy_#/ CS_B IO_Lxxy_#/ RDWR_B IO_Lxxy_#/ DOUT (O) BUSY/DOUT DUAL: Dual-purpose configuration pins (INIT_B has a pull-up resistor to ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 78: Pin Behavior After Power-Up, During Configuration (Continued) Serial Modes Master Pin Name <0:0:0> M1 M1=0 (I) M0 M0=0 (I) HSWAP_EN HSWAP_EN (I) JTAG: JTAG interface pins (pull-up resistor to VCCAUX always active during ...
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R Bitstream Options Table 79 lists the various bitstream options that affect pins on a Spartan-3 FPGA. The table shows the names of the affected pins, describes the function of the bitstream option, Table 79: Bitstream Options Affecting Spartan-3 Pins ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 79: Bitstream Options Affecting Spartan-3 Pins (Continued) Affected Pin Name(s) M0 After configuration, this bitstream option either pulls M0 to VCCAUX via a pull-up resistor, to ground via a pull-down resistor, or allows M0 ...
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R Selecting the Right Package Option Spartan-3 FPGAs are available in both quad-flat pack (QFP) and ball grid array (BGA) packaging options. While QFP packaging offers the lowest absolute cost, the BGA Table 81: Comparing Spartan-3 Packaging Options Characteristic Maximum ...
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Spartan-3 FPGA Family: Pinout Descriptions Power, Ground, and I/O by Package Each package has three separate voltage supply inputs—VCCINT, VCCAUX, and VCCO—and a common ground return, GND. The numbers of pins dedicated to these functions varies by package, as shown ...
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... FT256 XC3S400 FG320 XC3S1000 FG320 XC3S1500 FG320 XC3S400 FG456 XC3S1000 FG456 XC3S1500 FG456 XC3S2000 FG456 XC3S1000 FG676 XC3S1500 FG676 XC3S2000 FG676 XC3S4000 FG676 XC3S2000 FG900 XC3S4000 FG900 XC3S5000 FG900 XC3S4000 FG1156 XC3S5000 FG1156 Electronic versions of the package pinout tables and foot- prints are available for download from the Xilinx website ...
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... FG320 XC3S400 11.2 XC3S1000 9.8 XC3S1500 7.9 FG456 XC3S400 8.1 XC3S1000 6.7 XC3S1500 4.8 XC3S2000 3.7 FG676 XC3S1000 6.3 XC3S1500 4.9 XC3S2000 4.1 XC3S4000 3.7 FG900 XC3S2000 3.7 XC3S4000 3.2 XC3S5000 2.9 FG1156 XC3S4000 1.9 XC3S5000 1.9 122 age body (case) and the die junction temperature per watt of power consumption. The junction-to-board (θ ...
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R VQ100: 100-lead Very-thin Quad Flat Package The XC3S50 and the XC3S200 devices are available in the 100-lead very-thin quad flat package, VQ100. Both devices share a common footprint for this package as shown in Table 86 and Figure 42. ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 86: VQ100 Package Pinout XC3S50 XC3S200 Bank Pin Name 7 IO_L40N_7/VREF_7 7 IO_L40P_7 7 VCCO_7 N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A ...
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R VQ100 Footprint IO_L01P_7/VRN_7 1 2 IO_L01N_7/VRP_7 GND 3 IO_L21P_7 4 IO_L21N_7 5 6 VCCO_7 7 VCCAUX IO_L23P_7 8 IO_L23N_7 9 10 GND IO_L40P_7 11 IO_L40N_7/VREF_7 12 IO_L40P_6/VREF_6 13 IO_L40N_6 14 IO_L24P_6 15 IO_L24N_6/VREF_6 VCCINT 19 ...
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Spartan-3 FPGA Family: Pinout Descriptions CP132: 132-ball Chip-Scale Package The XC3S50 is available in the 132-ball chip-scale pack- age, CP132. The pinout and footprint for this package appear in Table 88 and Figure 44. All the package pins appear in ...
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R Table 88: CP132 Package Pinout Bank XC3S50 Pin Name 6 IO_L20N_6 6 IO_L20P_6 6 IO_L22N_6 6 IO_L22P_6 6 IO_L23N_6 6 IO_L23P_6 6 IO_L24N_6/VREF_6 6 IO_L24P_6 6 IO_L40N_6 6 IO_L40P_6/VREF_6 7 IO_L01N_7/VRP_7 7 IO_L01P_7/VRN_7 7 IO_L21N_7 7 IO_L21P_7 7 IO_L22N_7 ...
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Spartan-3 FPGA Family: Pinout Descriptions User I/Os by Bank Table 89 indicates how the 89 available user-I/O pins are distributed between the eight I/O banks on the CP132 pack- Table 89: User I/Os Per Bank for XC3S50 in CP132 Package ...
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R CP132 Footprint I/O VCCO_ A PROG_B TDI L01N_0 VRP_0 I/O I/O HSWAP_ B L01P_7 L01N_7 EN VRN_7 VRP_7 VCCO_ I/O C GND L01P_0 LEFT L21N_7 VRN_0 I/O I/O I/O D L22N_7 L22P_7 L21P_7 I/O I/O I/O ...
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Spartan-3 FPGA Family: Pinout Descriptions TQ144: 144-lead Thin Quad Flat Package The XC3S50, the XC3S200, and the XC3S400 are avail- able in the 144-lead thin quad flat package, TQ144. Conse- quently, there is only one footprint for this package as ...
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R Table 90: TQ144 Package Pinout (Continued) XC3S50 XC3S200 XC3S400 Bank Pin Name 5 IO_L28N_5/D6 5 IO_L28P_5/D7 5 IO_L31N_5/D4 5 IO_L31P_5/D5 5 IO_L32N_5/GCLK3 5 IO_L32P_5/GCLK2 6 IO_L01N_6/VRP_6 6 IO_L01P_6/VRN_6 6 IO_L20N_6 6 IO_L20P_6 6 IO_L21N_6 6 IO_L21P_6 6 IO_L22N_6 6 ...
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Spartan-3 FPGA Family: Pinout Descriptions User I/Os by Bank Table 91 indicates how the available user-I/O pins are dis- tributed between the eight I/O banks on the TQ144 pack- age. Table 91: User I/Os Per Bank in TQ144 Package Package ...
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R TQ144 Footprint IO_L01P_7/VRN_7 1 IO_L01N_7/VRP_7 2 X VCCO_LEFT 3 IO/VREF_7 4 IO_L20P_7 5 IO_L20N_7 6 IO_L21P_7 7 IO_L21N_7 8 GND 9 IO_L22P_7 10 IO_L22N_7 11 IO_L23P_7 12 IO_L23N_7 13 IO_L24P_7 14 IO_L24N_7 15 GND 16 IO_L40P_7 17 IO_L40N_7/VREF_7 18 ...
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Spartan-3 FPGA Family: Pinout Descriptions PQ208: 208-lead Plastic Quad Flat Pack The 208-lead plastic quad flat package, PQ208, supports three different Spartan-3 devices, including the XC3S50, the XC3S200, and the XC3S400. The footprints for the XC3S200 and XC3S400 are identical, ...
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R Table 92: PQ208 Package Pinout (Continued) XC3S200 XC3S50 XC3S400 Bank Pin Name Pin Name 2 IO_L23N_2/ IO_L23N_2/ VREF_2 VREF_2 2 IO_L23P_2 IO_L23P_2 2 IO_L24N_2 IO_L24N_2 2 IO_L24P_2 IO_L24P_2 2 N. IO_L39N_2 2 N. IO_L39P_2 2 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 92: PQ208 Package Pinout (Continued) XC3S200 XC3S50 XC3S400 Bank Pin Name Pin Name 5 IO_L32N_5/ IO_L32N_5/ GCLK3 GCLK3 5 IO_L32P_5/ IO_L32P_5/ GCLK2 GCLK2 5 VCCO_5 VCCO_5 5 VCCO_5 VCCO_5 6 N. IO/VREF_6 ...
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R Table 92: PQ208 Package Pinout (Continued) XC3S200 XC3S50 XC3S400 Bank Pin Name Pin Name N/A GND GND N/A VCCAUX VCCAUX N/A VCCAUX VCCAUX N/A VCCAUX VCCAUX N/A VCCAUX VCCAUX N/A VCCAUX VCCAUX N/A VCCAUX VCCAUX N/A VCCAUX VCCAUX N/A ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 94: User I/Os Per Bank for XC3S200 and XC3S400 in PQ208 Package Package Edge I/O Bank 0 Top 1 2 Right 3 4 Bottom 5 6 Left 7 138 All Possible I/O Pins by ...
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R DS099-4 (v2.2) May 25, 2007 Product Specification Spartan-3 FPGA Family: Pinout Descriptions www.xilinx.com 139 ...
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Spartan-3 FPGA Family: Pinout Descriptions PQ208 Footprint Left Half of Package (top view) XC3S50 (124 max. user I/O) I/O: Unrestricted, 72 general-purpose user I/O VREF: User I/O or input 16 voltage reference for bank N.C.: Unconnected pins for 17 XC3S50 ...
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R Bank 1 Bank 4 DS099-4 (v2.2) May 25, 2007 Product Specification Spartan-3 FPGA Family: Pinout Descriptions IO_L01N_2/VRP_2 156 IO_L01P_2/VRN_2 155 IO/VREF_2 ( ) 154 VCCO_2 153 IO_L19N_2 152 GND 151 IO_L19P_2 150 IO_L20N_2 149 IO_L20P_2 148 IO_L21N_2 147 IO_L21P_2 ...
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Spartan-3 FPGA Family: Pinout Descriptions FT256: 256-lead Fine-pitch Thin Ball Grid Array The 256-lead fine-pitch thin ball grid array package, FT256, supports three different Spartan-3 devices, including the XC3S200, the XC3S400, and the XC3S1000. The footprints for all three devices ...
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R Table 95: FT256 Package Pinout (Continued) XC3S200 XC3S400 XC3S1000 Bank Pin Name 2 IO_L39N_2 2 IO_L39P_2 2 IO_L40N_2 2 IO_L40P_2/VREF_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 IO_L01N_3/VRP_3 3 IO_L01P_3/VRN_3 3 IO_L16N_3 3 IO_L16P_3 3 IO_L17N_3 3 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 95: FT256 Package Pinout (Continued) XC3S200 XC3S400 XC3S1000 Bank Pin Name 5 VCCO_5 IO_L01N_6/VRP_6 6 IO_L01P_6/VRN_6 6 IO_L16N_6 6 IO_L16P_6 6 IO_L17N_6 6 IO_L17P_6/VREF_6 6 IO_L19N_6 6 IO_L19P_6 6 IO_L20N_6 6 ...
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R Table 95: FT256 Package Pinout (Continued) XC3S200 XC3S400 XC3S1000 Bank Pin Name N/A GND N/A GND N/A GND N/A GND N/A GND N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A ...
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Spartan-3 FPGA Family: Pinout Descriptions FT256 Footprint I TDI GND L01P_0 VREF_0 VRN_0 I/O I/O B PROG_B L01P_7 GND L01N_0 VRN_7 VRP_0 I/O I/O I/O HSWAP_ C L01N_7 L16P_7 L16N_7 EN VRP_7 VREF_7 I/O ...
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... R FG320: 320-lead Fine-pitch Ball Grid Array The 320-lead fine-pitch ball grid array package, FG320, supports three different Spartan-3 devices, including the XC3S400, the XC3S1000, and the XC3S1500. The foot- print for all three devices is identical, as shown in and Figure 47. The FG320 package array of solder balls minus the four center balls ...
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... I/O 4 M14 I/O 4 N14 I/O 4 M15 I/O 4 M16 VREF 4 M18 I/O 4 N17 I/O www.xilinx.com XC3S400 XC3S1000 FG320 XC3S1500 Pin Pin Name Number IO_L27N_3 L14 IO_L27P_3 L13 IO_L34N_3 L15 IO_L34P_3/VREF_3 L16 IO_L35N_3 L18 IO_L35P_3 L17 IO_L39N_3 K13 IO_L39P_3 K14 IO_L40N_3/VREF_3 K17 IO_L40P_3 ...
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... T3 DCI 7 T2 DCI VREF I/O 7 www.xilinx.com Spartan-3 FPGA Family: Pinout Descriptions XC3S400 XC3S1000 FG320 XC3S1500 Pin Pin Name Number IO_L21N_6 N4 IO_L21P_6 P4 IO_L22N_6 N5 IO_L22P_6 M5 IO_L23N_6 M3 IO_L23P_6 M4 IO_L24N_6/VREF_6 N2 IO_L24P_6 M1 IO_L27N_6 L6 IO_L27P_6 L5 IO_L34N_6/VREF_6 L3 IO_L34P_6 L4 IO_L35N_6 L2 IO_L35P_6 L1 IO_L39N_6 K5 IO_L39P_6 K4 IO_L40N_6 ...
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... L11 GND VCCAUX TDI L8 GND VCCAUX TDO L9 GND VCCAUX TMS M12 GND M7 GND N1 GND N18 GND T10 GND www.xilinx.com XC3S400 XC3S1000 FG320 XC3S1500 Pin Pin Name Number GND T9 GND U17 GND U2 GND V1 GND V13 GND V18 GND V6 VCCAUX B12 VCCAUX B7 VCCAUX ...
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R User I/Os by Bank Table 98 indicates how the available user-I/O pins are dis- tributed between the eight I/O banks on the FG320 pack- age. Table 98: User I/Os Per Bank in FG320 Package Maximum Package Edge I/O Bank ...
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Spartan-3 FPGA Family: Pinout Descriptions FG320 Footprint Bank I/O I/O I/O I/O A GND L01N_0 L01P_0 L15N_0 L15P_0 VRP_0 VRN_0 I/O I/O I/O I/O B GND L16P_7 VREF_0 L09N_0 L25N_0 VREF_7 I/O I/O I/O ...
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... XC3S400 that maps to a user-I/O pin on the XC3S1000, XC3S1500, and XC3S2000. If the table entry is shaded tan, then the unconnected pin on the XC3S400 maps to a VREF-type pin on the XC3S1000, the XC3S1500, or the XC3S2000 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 1 IO/VREF_1 IO/VREF_1 1 N. IO/VREF_1 1 IO_L01N_1/ IO_L01N_1/ VRP_1 VRP_1 1 IO_L01P_1/ IO_L01P_1/ VRN_1 VRN_1 1 IO_L06N_1/ ...
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R Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 2 IO_L40P_2/ IO_L40P_2/ VREF_2 VREF_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 4 IO_L24P_4 IO_L24P_4 4 IO_L25N_4 IO_L25N_4 4 IO_L25P_4 IO_L25P_4 4 IO_L27N_4/ IO_L27N_4/ DIN/D0 DIN/D0 4 IO_L27P_4/ IO_L27P_4 ...
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R Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 6 IO_L19N_6 IO_L19N_6 6 IO_L19P_6 IO_L19P_6 6 IO_L20N_6 IO_L20N_6 6 IO_L20P_6 IO_L20P_6 6 IO_L21N_6 IO_L21N_6 6 IO_L21P_6 IO_L21P_6 6 IO_L22N_6 IO_L22N_6 6 IO_L22P_6 IO_L22P_6 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 7 IO_L40N_7/ IO_L40N_7/ VREF_7 VREF_7 7 IO_L40P_7 IO_L40P_7 7 VCCO_7 VCCO_7 7 VCCO_7 VCCO_7 7 VCCO_7 VCCO_7 7 VCCO_7 VCCO_7 ...
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... Table 100: User I/Os Per Bank for XC3S400 in FG456 Package I/O Maximum Edge Bank 0 Top 1 2 Right 3 4 Bottom 5 6 Left 7 Table 101: User I/Os Per Bank for XC3S1000, XC3S1500, and XC3S2000 in FG456 Package Maximum Edge I/O Bank 0 Top 1 2 Right 3 4 Bottom 5 6 Left 7 DS099-4 (v2.2) May 25, 2007 ...
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... I/O VREF: User I/O or input 32 voltage reference for bank N.C.: Unconnected pins for 69 XC3S400 ( ) XC3S1000, XC3S1500, XC3S2000 (333 max user I/O) I/O: Unrestricted, 261 general-purpose user I/O VREF: User I/O or input 36 voltage reference for bank N.C.: No unconnected pins ...
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R Bank I/O I/O I/O I/O L22N_1 I/O VCCAUX L30N_1 L28N_1 L25P_1 I/O I/O I/O I/O I/O I/O L22P_1 L32N_1 L30P_1 L28P_1 L25N_1 L16N_1 GCLK5 I/O I/O I/O I/O L19N_1 L32P_1 GND VCCO_1 ...
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... XC3S1000 or XC3S1500 that maps to a user-I/O pin on the XC3S2000 and XC3S4000. If the table entry is shaded tan, then the unconnected pin on either the XC3S1000 or XC3S1500 maps to a VREF-type pin on the XC3S2000 and XC3S4000. If the other VREF pins in the bank all connect to a voltage reference to support a special I/O standard, then also connect the N ...
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... C21 I/O 1 VCCO_1 D21 I/O 1 VCCO_1 A21 I/O 1 VCCO_1 B21 I/O 1 VCCO_1 D20 I/O www.xilinx.com XC3S2000 FG676 XC3S1500 XC3S4000 Pin Type Pin Name Pin Name Number IO_L09P_1 IO_L09P_1 E20 IO_L10N_1/ IO_L10N_1/ A20 VREF VREF_1 VREF_1 IO_L10P_1 IO_L10P_1 B20 IO_L11N_1 IO_L11N_1 E19 ...
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... IO_L03N_3 I/O J25 3 IO_L03P_3 I/O K21 3 N. VREF 3 N. K22 I K23 I/O www.xilinx.com XC3S2000 FG676 XC3S1500 XC3S4000 Pin Type Pin Name Pin Name Number IO_L24P_2 IO_L24P_2 K24 IO_L26N_2 IO_L26N_2 K25 IO_L26P_2 IO_L26P_2 K26 IO_L27N_2 IO_L27N_2 L19 IO_L27P_2 IO_L27P_2 L20 ...
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... I/O 4 IO_L08P_4 R24 I/O 4 IO_L09N_4 T23 I/O 4 IO_L09P_4 R26 I/O 4 IO_L10N_4 R25 VREF 4 IO_L10P_4 www.xilinx.com XC3S2000 FG676 XC3S1500 XC3S4000 Pin Type Pin Name Pin Name Number IO_L35N_3 IO_L35N_3 P20 IO_L35P_3 IO_L35P_3 P19 IO_L38N_3 IO_L38N_3 P22 IO_L38P_3 IO_L38P_3 P21 IO_L39N_3 IO_L39N_3 P24 ...
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... IO_L15N_5 5 IO_L15P_5 AF14 GCLK 5 IO_L16N_5 5 IO_L16P_5 AD16 VCCO 5 N. AD20 VCCO 5 N. U14 VCCO www.xilinx.com XC3S2000 FG676 XC3S1500 XC3S4000 Pin Type Pin Name Pin Name Number VCCO_4 VCCO_4 V14 VCCO VCCO_4 VCCO_4 V15 VCCO VCCO_4 VCCO_4 V16 VCCO VCCO_4 VCCO_4 W17 ...
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... IO_L29P_6 AD1 DCI 6 IO_L31N_6 6 IO_L31P_6 AB4 I/O 6 IO_L32N_6 AB3 I/O 6 IO_L32P_6 AC2 VREF 6 IO_L33N_6 www.xilinx.com XC3S2000 FG676 XC3S1500 XC3S4000 Pin Type Pin Name Pin Name Number IO_L03P_6 IO_L03P_6 AC1 IO_L05N_6 IO_L05N_6 AB2 IO_L05P_6 IO_L05P_6 AB1 IO_L06N_6 IO_L06N_6 Y7 IO_L06P_6 IO_L06P_6 Y6 IO_L07N_6 IO_L07N_6 ...
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... I/O 7 IO_L40P_7 H7 VREF 7 VCCO_7 G1 I/O 7 VCCO_7 G2 I/O 7 VCCO_7 J6 I/O 7 VCCO_7 H5 7 VCCO_7 VREF 7 VCCO_7 www.xilinx.com XC3S2000 FG676 XC3S1500 XC3S4000 Pin Type Pin Name Pin Name Number IO_L17N_7 IO_L17N_7 H3 IO_L17P_7 IO_L17P_7 H4 IO_L19N_7/ IO_L19N_7/ H1 VREF VREF_7 VREF_7 IO_L19P_7 IO_L19P_7 H2 IO_L20N_7 IO_L20N_7 K7 IO_L20P_7 IO_L20P_7 J7 ...
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... M17 N/A VCCAUX GND M23 N/A VCCAUX GND N11 N/A VCCAUX GND N12 N/A VCCAUX GND www.xilinx.com XC3S2000 FG676 XC3S1500 XC3S4000 Pin Type Pin Name Pin Name Number GND GND N13 GND GND GND N14 GND GND GND N15 GND GND ...
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... U9 VCCINT AUX U10 VCCINT Notes: U17 VCCINT 1. XC3S1500 balls D25 and F25 are not VREF pins although they are designated as such design uses an IOSTANDARD requiring U18 VCCINT VREF in bank 2 then apply the workaround in V9 20519 VCCINT 2. XC3S4000 is pin compatible but uses alternate differential pairs on ...
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... R Table 104: User I/Os Per Bank for XC3S1500 in FG676 Package I/O Maximum Edge Bank 0 Top 1 2 Right 3 4 Bottom 5 6 Left 7 Table 105: User I/Os Per Bank for XC3S2000 and XC3S4000 in FG676 Package Maximum Edge I/O Bank 0 Top 1 2 Right 3 4 Bottom ...
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... I/O) I/O: Unrestricted, 403 general-purpose user I/O VREF: User I/O or input 48 voltage reference for bank N.C.: Unconnected pins for 2 XC3S1500 ( ) XC3S2000, XC3S4000 (489 max user I/O) I/O: Unrestricted, 405 general-purpose user I/O VREF: User I/O or input 48 voltage reference for bank N ...
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R Bank I/O I/O I/O I/O L26N_1 L23N_1 VCCAUX I/O L10N_1 L29N_1 L15N_1 VREF_1 I/O I/O I/O I/O I/O I/O L26P_1 L23P_1 L18N_1 L32N_1 L29P_1 L15P_1 L10P_1 GCLK5 I/O I/O I/O I/O I/O ...
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Spartan-3 FPGA Family: Pinout Descriptions FG900: 900-lead Fine-pitch Ball Grid Array The 900-lead fine-pitch ball grid array package, FG900, supports three different Spartan-3 devices, including the XC3S2000, the XC3S4000, and the XC3S5000. The foot- prints for the XC3S4000 and XC3S5000 ...
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R Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name 0 IO_L28N_0 IO_L28N_0 0 IO_L28P_0 IO_L28P_0 0 IO_L29N_0 IO_L29N_0 0 IO_L29P_0 IO_L29P_0 0 IO_L30N_0 IO_L30N_0 0 IO_L30P_0 IO_L30P_0 0 IO_L31N_0 IO_L31N_0 0 IO_L31P_0/ IO_L31P_0/ VREF_0 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name 1 IO_L25N_1 IO_L25N_1 1 IO_L25P_1 IO_L25P_1 1 IO_L26N_1 IO_L26N_1 1 IO_L26P_1 IO_L26P_1 1 IO_L27N_1 IO_L27N_1 1 IO_L27P_1 IO_L27P_1 1 IO_L28N_1 IO_L28N_1 ...
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R Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name 2 IO_L28P_2 IO_L28P_2 2 IO_L29N_2 IO_L29N_2 2 IO_L29P_2 IO_L29P_2 2 IO_L31N_2 IO_L31N_2 2 IO_L31P_2 IO_L31P_2 2 IO_L32N_2 IO_L32N_2 2 IO_L32P_2 IO_L32P_2 2 IO_L33N_2 IO_L33N_2 2 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name 3 IO_L23N_3 IO_L23N_3 3 IO_L23P_3/ IO_L23P_3/ VREF_3 VREF_3 3 IO_L24N_3 IO_L24N_3 3 IO_L24P_3 IO_L24P_3 3 IO_L26N_3 IO_L26N_3 3 IO_L26P_3 IO_L26P_3 3 ...
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R Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name 4 IO_L15N_4 IO_L15N_4 4 IO_L15P_4 IO_L15P_4 4 IO_L16N_4 IO_L16N_4 4 IO_L16P_4 IO_L16P_4 4 IO_L17N_4 IO_L17N_4 4 IO_L17P_4 IO_L17P_4 4 IO_L18N_4 IO_L18N_4 4 IO_L18P_4 IO_L18P_4 4 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name 5 IO_L10N_5/ IO_L10N_5/ VRP_5 VRP_5 5 IO_L10P_5/ IO_L10P_5/ VRN_5 VRN_5 5 IO_L11N_5/ IO_L11N_5/ VREF_5 VREF_5 5 IO_L11P_5 IO_L11P_5 5 IO_L12N_5 IO_L12N_5 ...
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R Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name 6 IO_L07N_6 IO_L07N_6 6 IO_L07P_6 IO_L07P_6 6 IO_L08N_6 IO_L08N_6 6 IO_L08P_6 IO_L08P_6 6 IO_L09N_6/ IO_L09N_6/ VREF_6 VREF_6 6 IO_L09P_6 IO_L09P_6 6 IO_L10N_6 IO_L10N_6 6 IO_L10P_6 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name 7 IO_L04N_7 IO_L04N_7 7 IO_L04P_7 IO_L04P_7 7 IO_L05N_7 IO_L05N_7 7 IO_L05P_7 IO_L05P_7 7 IO_L06N_7 IO_L06N_7 7 IO_L06P_7 IO_L06P_7 7 IO_L07N_7 IO_L07N_7 ...
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R Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND ...
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R Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name VCCAUX PROG_B PROG_B VCCAUX TCK TCK VCCAUX TDI TDI VCCAUX TDO TDO VCCAUX TMS TMS Table 107: User I/Os Per Bank for XC3S2000 in FG900 ...
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Spartan-3 FPGA Family: Pinout Descriptions FG900 Footprint Left Half of FG900 Package (top view) XC3S2000 (565 max. user I/O) I/O: Unrestricted, 481 general-purpose user I/O VREF: User I/O or input 48 voltage reference for bank N.C.: Unconnected pins for 68 ...
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R Bank I/O I/O I/O I/O L39N_1 I/O GND GND L26N_1 L21N_1 L15N_1 L11N_1 I/O I/O I/O I/O I/O I/O I/O L39P_1 L32N_1 L17N_1 L28N_1 L26P_1 L21P_1 L15P_1 L11P_1 VREF_1 GCLK5 I/O ...
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Spartan-3 FPGA Family: Pinout Descriptions FG1156: 1156-lead Fine-pitch Ball Grid Array The 1,156-lead fine-pitch ball grid array package, FG1156, supports two different Spartan-3 devices, namely the XC3S4000 and the XC3S5000. The XC3S4000, however, has fewer I/O pins, which consequently results ...
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R Table 109: FG1156 Package Pinout (Continued) XC3S4000 XC3S5000 Bank Pin Name Pin Name 0 IO_L16N_0 IO_L16N_0 0 IO_L16P_0 IO_L16P_0 0 IO_L17N_0 IO_L17N_0 0 IO_L17P_0 IO_L17P_0 0 IO_L18N_0 IO_L18N_0 0 IO_L18P_0 IO_L18P_0 0 IO_L19N_0 IO_L19N_0 0 IO_L19P_0 IO_L19P_0 0 IO_L20N_0 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 109: FG1156 Package Pinout (Continued) XC3S4000 XC3S5000 Bank Pin Name Pin Name IO/VREF_1 IO/VREF_1 1 IO/VREF_1 IO/VREF_1 1 IO/VREF_1 IO/VREF_1 1 IO_L01N_1/ IO_L01N_1/ VRP_1 VRP_1 1 IO_L01P_1/ IO_L01P_1/ VRN_1 VRN_1 ...
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R Table 109: FG1156 Package Pinout (Continued) XC3S4000 XC3S5000 Bank Pin Name Pin Name 1 IO_L37N_1 IO_L37N_1 1 IO_L37P_1 IO_L37P_1 1 IO_L38N_1 IO_L38N_1 1 IO_L38P_1 IO_L38P_1 1 IO_L39N_1 IO_L39N_1 1 IO_L39P_1 IO_L39P_1 1 IO_L40N_1 IO_L40N_1 1 IO_L40P_1 IO_L40P_1 1 VCCO_1 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 109: FG1156 Package Pinout (Continued) XC3S4000 XC3S5000 Bank Pin Name Pin Name 2 IO_L29N_2 IO_L29N_2 2 IO_L29P_2 IO_L29P_2 2 IO_L30N_2 IO_L30N_2 2 IO_L30P_2 IO_L30P_2 2 IO_L31N_2 IO_L31N_2 2 IO_L31P_2 IO_L31P_2 2 IO_L32N_2 IO_L32N_2 2 ...
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R Table 109: FG1156 Package Pinout (Continued) XC3S4000 XC3S5000 Bank Pin Name Pin Name 3 IO_L11P_3 IO_L11P_3 3 IO_L12N_3 IO_L12N_3 3 IO_L12P_3 IO_L12P_3 3 IO_L13N_3/ IO_L13N_3/ VREF_3 VREF_3 3 IO_L13P_3 IO_L13P_3 3 IO_L14N_3 IO_L14N_3 3 IO_L14P_3 IO_L14P_3 3 IO_L15N_3 IO_L15N_3 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 109: FG1156 Package Pinout (Continued) XC3S4000 XC3S5000 Bank Pin Name Pin Name 3 VCCO_3 VCCO_3 3 VCCO_3 VCCO_3 3 VCCO_3 VCCO_3 3 VCCO_3 VCCO_3 3 VCCO_3 VCCO_3 ...
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R Table 109: FG1156 Package Pinout (Continued) XC3S4000 XC3S5000 Bank Pin Name Pin Name 4 IO_L27P_4/ IO_L27P_4 IO_L28N_4 IO_L28N_4 4 IO_L28P_4 IO_L28P_4 4 IO_L29N_4 IO_L29N_4 4 IO_L29P_4 IO_L29P_4 4 IO_L30N_4/ IO_L30N_4 IO_L30P_4/ IO_L30P_4/ D3 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 109: FG1156 Package Pinout (Continued) XC3S4000 XC3S5000 Bank Pin Name Pin Name 5 IO_L09N_5 IO_L09N_5 5 IO_L09P_5 IO_L09P_5 5 IO_L10N_5/ IO_L10N_5/ VRP_5 VRP_5 5 IO_L10P_5/ IO_L10P_5/ VRN_5 VRN_5 5 IO_L11N_5/ IO_L11N_5/ VREF_5 VREF_5 5 ...
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R Table 109: FG1156 Package Pinout (Continued) XC3S4000 XC3S5000 Bank Pin Name Pin Name 5 VCCO_5 VCCO_5 5 VCCO_5 VCCO_5 5 VCCO_5 VCCO_5 5 VCCO_5 VCCO_5 IO_L01N_6/ ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 109: FG1156 Package Pinout (Continued) XC3S4000 XC3S5000 Bank Pin Name Pin Name 6 IO_L36N_6 IO_L36N_6 6 IO_L36P_6 IO_L36P_6 6 IO_L37N_6 IO_L37N_6 6 IO_L37P_6 IO_L37P_6 6 IO_L38N_6 IO_L38N_6 6 IO_L38P_6 IO_L38P_6 6 IO_L39N_6 IO_L39N_6 6 ...
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R Table 109: FG1156 Package Pinout (Continued) XC3S4000 XC3S5000 Bank Pin Name Pin Name 7 IO_L20N_7 IO_L20N_7 7 IO_L20P_7 IO_L20P_7 7 IO_L21N_7 IO_L21N_7 7 IO_L21P_7 IO_L21P_7 7 IO_L22N_7 IO_L22N_7 7 IO_L22P_7 IO_L22P_7 7 IO_L23N_7 IO_L23N_7 7 IO_L23P_7 IO_L23P_7 7 IO_L24N_7 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 109: FG1156 Package Pinout (Continued) XC3S4000 XC3S5000 Bank Pin Name Pin Name N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A ...