KSZ8995MI Micrel Inc, KSZ8995MI Datasheet - Page 27

• Manufacturer Part Number: KSZ8995MI
• Description: 5 Port 10/100 Switch With PHY And Frame Buffers
• Manufacturer: Micrel Inc

Specifications of KSZ8995MI

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.9/2.6/3.6V
• Operating Supply Voltage (min): 1.7/2.4/3V
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-2127; KSZ8995MI

June 2009
KS8995M
MII signal
MTXEN
MTXER
MTXD3
MTXD2
MTXD1
MTXD0
MTXC
MCOL
MCRS
MRXDV
MRXER
MRXD3
MRXD2
MRXD1
MRXD0
MRXC
MDC
MDIO
PHY Mode Connection
External
MAC
MTXEN
MTXER
MTXD3
MTXD2
MTXD1
MTXD0
MTXC
MCOL
MCRS
MRXDV
MRXER
MRXD3
MRXD2
MRXD1
MRXD0
MRXC
KS8995M
Signal
SMTXEN
SMTXER
SMTXD[3]
SMTXD[2]
SMTXD[1]
SMTXD[0]
SMTXC
SCOL
SCRS
SMRXDV
Not used
SMRXD[3]
SMRXD[2]
SMRXD[1]
SMRXD[0]
SMRXC
Description
Transmit enable
Transmit error
Transmit data bit 3
Transmit data bit 2
Transmit data bit 1
Transmit data bit 0
Transmit clock
Collision detection
Carrier sense
Receive data valid
Receive error
Receive data bit 3
Receive data bit 2
Receive data bit 1
Receive data bit 0
Receive clock
Management data clock
Management data I/O
Table 1. MII–P5 Signals (PHY Mode)
Description
Transmit enable
Transmit error
Transmit data bit 3
Transmit data bit 2
Transmit data bit 1
Transmit data bit 0
Transmit clock
Collision detection
Carrier sense
Receive data valid
Receive error
Receive data bit 3
Receive data bit 2
Receive data bit 1
Receive data bit 0
Receive clock
Table 2. MII–SW Signals
27
MAC Mode Connection
External
PHY
MTXEN
MTXER
MTXD3
MTXD2
MTXD1
MTXD0
MTXC
MCOL
MCRS
MRXDV
MRXER
MRXD3
MRXD2
MRXD1
MRXD0
MRXC
KS8995M signal
PMTXEN
PMTXER
PMTXD[3]
PMTXD[2]
PMTXD[1]
PMTXD[0]
PMTXC
PCOL
PCRS
PMRXDV
PMRXER
PMRXD[3]
PMRXD[2]
PMRXD[1]
PMRXD[0]
PMRXC
MDC
MDIO
KS8995M
Signal
SMRXDV
Not used
SMRXD[3]
SMRXD[2]
SMRXD[1]
SMRXD[0]
SMRXC
SCOL
SCRS
SMTXEN
SMTXER
SMTXD[3]
SMTXD[2]
SMTXD[1]
SMTXD[0]
SMTXC
M9999-062309
Micrel, Inc.