KSZ8995MI Micrel Inc, KSZ8995MI Datasheet - Page 38

• Manufacturer Part Number: KSZ8995MI
• Description: 5 Port 10/100 Switch With PHY And Frame Buffers
• Manufacturer: Micrel Inc

Specifications of KSZ8995MI

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.9/2.6/3.6V
• Operating Supply Voltage (min): 1.7/2.4/3V
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-2127; KSZ8995MI

KS8995M
MII Management Interface (MIIM)
A standard MIIM interface is provided for all five PHY devices in the KS8995M. An external device with MDC/MDIO capability
is able to read PHY status or to configure PHY settings. For details on the MIIM interface standard please reference the IEEE
802.3 specification (section 22.2.4.5). The MIIM interface does not have access to all the configuration registers in the
KS8995M. It can only access the standard MII registers. See “MIIM Registers.” The SPI interface, on the other hand, can be
used to access the entire KS8995M feature set.
M9999-062309
SPIS_N
SPIS_N
SPIS_N
SPIS_N
SPIQ
SPIQ
SPIC
SPID
SPIC
SPID
SPIC
SPID
SPIQ
SPIC
SPID
SPIQ
D7
X
X
D7
X
D6
X
0
D6
0
D5
X
0
D5
READ COMMAND
Byte 2
0
D4
0
X
D4
Byte 2
WRITE COMMAND
0
D3
0
X
D4
0
D2
0
X
D2
0
D1
X
D1
0
0
Figure 10. SPI Multiple Write
Figure 11. SPI Multiple Read
D0
X
1
D0
1
D7
X
1
D7
0
A7 A6 A5 A4 A3 A2 A1 A0
D6
X
D6
A7 A6 A5 A4 A3 A2 A1 A0
D5
X
D5
READ ADDRESS
Byte 3
38
Byte 3 ...
D4
X
D4
WRITE ADDRESS
D3
X
D3
D2
X
D2
D1
X
D1
D0
X
D0
D7
X
D7
X
D7
D7
D6
X
D6
X
D6
D6
D5
X
D5
X
Byte 1
D5
D5
Byte N
D4
X
D4
X
D4
D4
Byte N
Byte 1
D3
X
D3
X
D3
D3
D2
X
D2
X
D2
D2
D1
X
D1
X
D1
D1
D0
X
D0
X
D0
D0
Micrel, Inc.
June 2009