5M160ZM100A5N Altera, 5M160ZM100A5N Datasheet - Page 77
5M160ZM100A5N
Manufacturer Part Number
5M160ZM100A5N
Description
ALTERA
Manufacturer
Altera
Series
MAX® Vr
Specifications of 5M160ZM100A5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
160
Number Of Macrocells
128
Number Of Gates
-
Number Of I /o
79
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Vendor undefined / RoHS Compliant
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Chapter 3: DC and Switching Characteristics for MAX V Devices
Document Revision History
Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 2 of 2)
Document Revision History
Table 3–42. Document Revision History
January 2011 Altera Corporation
t
Notes to
(1) Minimum clock period specified for 10 pF load on the TDO pin. Larger loads on TDO degrades the maximum TCK frequency.
(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V LVTTL/LVCMOS and
January 2011
December 2010
JSXZ
1.5-V LVCMOS operation, the t
Symbol
Date
Table
3–41:
Table 3–42
Update register valid output to high impedance
Version
1.1
1.0
JPSU
minimum is 6 ns and t
lists the revision history for this chapter.
Updated
Initial release.
Parameter
Table
JPCO
, t
3–37,
JPZX
, and t
Table
JPXZ
3–38,
are maximum values at 35 ns.
Table
Changes
3–39, and
Min
—
Table
3–40.
Max
25
MAX V Device Handbook
Unit
ns
3–29
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