5M160ZM100A5N Altera, 5M160ZM100A5N Datasheet - Page 98
5M160ZM100A5N
Manufacturer Part Number
5M160ZM100A5N
Description
ALTERA
Manufacturer
Altera
Series
MAX® Vr
Specifications of 5M160ZM100A5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
160
Number Of Macrocells
128
Number Of Gates
-
Number Of I /o
79
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Vendor undefined / RoHS Compliant
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6–4
MAX V Device Handbook
JTAG Block
f
f
For more information about JTAG BST, refer to the
MAX V Devices
If you issue either the USER0 or USER1 instruction to the JTAG test access port (TAP)
controller, the MAX V JTAG block feature allows you to access the JTAG TAP
controller and state signals. The USER0 and USER1 instructions bring the JTAG
boundary-scan chain (TDI) through the user logic instead of the boundary-scan cells
(BSCs) of MAX V devices. Each USER instruction allows for one unique user-defined
JTAG chain into the logic array.
Parallel Flash Loader
MAX V devices have the ability to interface JTAG to non-JTAG devices and are
suitable to use with the general flash memory devices that require programming
during the in-circuit test. You can use the flash memory devices for FPGA
configuration or be part of the system memory. In many cases, you can use the
MAX V device as a bridge device that controls configuration between FPGA and flash
devices. Unlike ISP-capable CPLDs, bulk flash devices do not have JTAG TAP pins or
connections. For small flash devices, it is common to use the serial JTAG scan chain of
a connected device to program the non-JTAG flash device but this is slow, inefficient,
and impractical for large parallel flash devices. Using the MAX V JTAG block as a
parallel flash loader (PFL) with the Quartus II software to program and verify flash
contents provides a fast and cost-effective means of in-circuit programming during
testing.
For more information about PFL, refer to the
Guide.
chapter.
Chapter 6: JTAG and In-System Programmability in MAX V Devices
Parallel Flash Loader Megafunction User
JTAG Boundary-Scan Testing for
IEEE Std. 1149.1 Boundary-Scan Support
December 2010 Altera Corporation
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