A4940KLPTR-T Allegro Microsystems Inc, A4940KLPTR-T Datasheet - Page 14

• Manufacturer Part Number: A4940KLPTR-T
• Description: FULL BRIDGE MOSFET PRE-DRIVER
• Manufacturer: Allegro Microsystems Inc

Specifications of A4940KLPTR-T

• Configuration: H Bridge
• Input Type: Non-Inverting
• Delay Time: 35ns
• Number Of Configurations: 1
• Number Of Outputs: 4
• Voltage - Supply: 5.5 V ~ 50 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Peak: -
• High Side Voltage - Max (bootstrap): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 620-1319-2

A4940
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
Copyright ©2009, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
24X
0.10
C
0.30
0.19
24
1
2
A
7.80±0.10
4.32 NOM
Package LP 24-Pin TSSOP with Exposed Thermal Pad
0.65 BSC
B
For the latest version of this document, visit our website:
3 NOM
0.15
0.00
Automotive Full Bridge MOSFET Driver
4.40±0.10
SEATING
PLANE
1.20 MAX
www.allegromicro.com
6.40±0.20
C
C
A Terminal #1 mark area
B
Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
For Reference Only; not for tooling use (reference MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Exposed thermal pad (bottom surface); dimensions may vary with device
GAUGE PLANE
0.25 BSC
8º
0º
0.60 ±0.15
SEATING PLANE
0.20
0.09
1.00 REF
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
1.65
C
0.45
PCB Layout Reference View
4.32
0.65
3.00
6.10
14