AD723ARU-REEL Analog Devices Inc, AD723ARU-REEL Datasheet - Page 8

• Manufacturer Part Number: AD723ARU-REEL
• Description: IC,TV/VIDEO CIRCUIT,Color Encoder Circuit,CMOS,TSSOP,28PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of AD723ARU-REEL

• Rohs Status: RoHS non-compliant
• Applications: Cameras, Internet Appliances, Set-Top Boxes
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Voltage - Supply, Analog: -

AD723
THEORY OF OPERATION
The AD723 is a predominantly analog design, with digital logic
control of timing. This timing logic is driven by an external
frequency reference at four times the color subcarrier frequency,
input into the 4FSC pin of the AD723. This frequency should
be 14.318 180 MHz for NTSC encoding, and 17.734 475 MHz
for PAL encoding. The 4FSC input accepts standard 3 V CMOS
logic levels. The duty cycle of this input clock is not critical, but
a fast-edged clock should be used to prevent excessive jitter in
the timing.
The AD723 accepts two common sync standards, composite
sync or separate horizontal and vertical syncs. To use an exter-
nal composite sync, a logic high signal is input to the VSYNC
pin and the composite sync is input to the HSYNC pin. If sepa-
rate horizontal and vertical syncs are available, the horizontal
sync can be input to the HSYNC pin and vertical sync to the
VSYNC pin. Internally, the device XNORs the two sync inputs
to combine them into one negative-going composite sync.
The AD723 detects the falling sync pulse edges, and times their
width. A sync pulse of standard horizontal width will cause the
insertion of a colorburst vector into the chroma modulators at
the proper time. A sync pulse outside the detection range will
cause suppression of the color burst, and the device will enter its
vertical blanking mode. During this mode, the on-chip RC time
constants are verified using the input frequency reference, and
the filter cutoff frequencies are retuned as needed.
The component color inputs, RIN, GIN, and BIN, receive
analog signals specifying the desired active video output. The
full-scale range of the inputs is 0.714 mV (for either NTSC
or PAL operation). External black level is not important as
these inputs are terminated externally, and then ac-coupled to
the AD723.
The AD723 contains on-chip RGB input clamps to restore the
dc level on-chip to match its single supply signal path. This dc
HSYNC
TERMINATION
TERM
4FSC
VSYNC
TRIPLE INPUT
RT
GT
BT
RIN
GIN
BIN
GND
GND
GND
CLAMP
CLAMP
CLAMP
DC
DC
DC
RGB-TO-YUV
ENCODING
MATRIX
QUADRATURE
SEPARATOR
DECODER
SYNC
Y
U
V
4-POLE
CSYNC
4-POLE
4-POLE
BURST
BURST
LPF
LPF
LPF
FSC
BURST
CSYNC
restore timing is coincident with the burst flag, starting approxi-
mately 5.5 ms after the falling sync edge and lasting for 2.5 ms.
During this time, the device should be driven with a black input.
Following the dc clamps, the RGB inputs are buffered and
split into two signal paths for constructing the luminance and
chrominance outputs.
Luminance Signal Path
The luminance path begins with the luma (Y) matrix. This
matrix combines the RGB inputs to form the brightness infor-
mation in the output video. The inputs are combined by the
standard transformation
This equation describes the sensitivity of the human eye to the
individual component colors, combining them into one value of
brightness. The equation is balanced so that full-scale RGB
inputs give a full-scale Y output.
Following the luma matrix, the composite sync is added. The
user-supplied sync (from the HSYNC and VSYNC inputs) is
latched into the AD723 at half the master clock rate, gating a
sync pulse into the luminance signal. With the exception of
transitioning on the clock edges, the output sync timing will be
in the same format as the input sync timing.
In order to be time-aligned with the filtered chrominance signal
path, the luma signal must be delayed before it is output. The
AD723 uses a sampled delay line to achieve this delay.
Following the luma matrix, and prior to this delay line, a prefilter
removes higher frequencies from the luma signal to prevent
aliasing by the sampled delay line. This four-pole Bessel low-
pass filter has a –3 dB frequency of 8 MHz for NTSC, 10 MHz
for PAL. This bandwidth is high to leave margin for subsequent
filters which combine to set the overall luma –3 dB bandwidth. A
fourth order filter ensures adequate rejection at high frequencies.
SIN
MODULATORS
8FSC CLK
BALANCED
COS
Y = 0.299 × R + 0.587 × G + 0.114 × B
DELAY LINE
STND
LUMA
AD723
CE
4-POLE
4-POLE
LPF
LPF
TV DETECT
LUMA
TRAP
CURRENT OUTPUT DRIVERS
WITH SMART LOAD DETECT
RESISTORS
CHROMINANCE
GAIN SET
COMPOSITE
LUMINANCE
Y TRAP
CVSET
YSET
CSET
CV
C
Y