AD723 Analog Devices, AD723 Datasheet
AD723
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AD723 Summary of contents
Page 1
... DVD, is supported through choice of RGB output clocks and sync intervals. An optional luminance trap (YTRAP) provides a means of reducing cross color artifacts due to subcarrier frequency infor- mation in the Y signal. The AD723 is available in a 28-lead TSSOP package and is capable of operation from supplies of 2 5.5 V. FUNCTIONAL BLOCK DIAGRAM Y 4-POLE ...
Page 2
... AD723–SPECIFICATIONS inputs terminated with 75 . Outputs configured in active termination mode, 75 Parameter SIGNAL INPUTS (RIN, GIN, BIN) Input Amplitude Clamp Level Input Resistance Input Capacitance TERMINATION SWITCH CHARACTERISTICS (RT, GT, BT) Input Capacitance Switch On Resistance LOGIC INPUTS (STND, SA, CE, TERM, SYNC, 4FSC) Logic LO Input Voltage ...
Page 3
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD723 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 4
... AD723 Pin Mnemonic Description 1 STND Encoding Standard Pin. A Logic HIGH signal is used for NTSC encoding, a Logic LOW signal signifies PAL When SA is high, phase alternation accompanies NTSC bandwidths and timing for support of PAL (M) and “combination N” standards used in South America. ...
Page 5
... NOISE REDUCTION: 15.05dB SYSTEM LINE L147 F1 ANGLE (DEG) 0.0 APL = 51.0% GAIN 0.750 –2.499dB 525 LINE NTSC BURST FROM SOURCE SOUND IN SYNC OFF AD723 COMPOSITE SONY VIDEO MONITOR MODEL PVM-1354Q 75 TEKTRONIX VM700A WAVEFORM MONITOR APL = 51.2% 625 LINE PAL NO FILTERING SLOW CLAMP TO 0 ...
Page 6
... AD723 1.0 APL = 46.6% 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00V @ 6.63 s 0.5 0.0 –0 200mV 1.0 APL = 34.8% 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00V @ 6.72 s 100 0.5 50 0.0 0 –50 –0 200mV 1 s ...
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... MAX = 0.61 p-p/MAX = 0.60 DIFFERENTIAL GAIN (%) 0.30 0.61 0.00 0.2 0.1 0.0 –0.1 –0.2 DIFFERENTIAL PHASE (deg) MAX = 0.24 pk-pk = 0.24 0.24 0.15 0.00 0.20 0.15 0.10 0.05 0.00 –0.05 5TH 6TH 1ST AD723 APL = 51.3% 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00V @ 6. 5.70 s 2.24 s 4.67 s 277mV 72ns 256 > Wfm — MOD 5 STEP MIN = –0.08 MAX = 0.18 0.05 –0.08 –0.02 0.06 MIN = 0.00 MAX = 0 ...
Page 8
... Following the luma matrix, the composite sync is added. The user-supplied sync (from the HSYNC and VSYNC inputs) is latched into the AD723 at half the master clock rate, gating a sync pulse into the luminance signal. With the exception of transitioning on the clock edges, the output sync timing will be in the same format as the input sync timing ...
Page 9
... This will change the V-vector phase in PAL mode every horizontal line. By driving the AD723 with an odd number of sync edges per field, any indi- vidual line will flip phase each field as required by the standard. In order to suppress the carriers in the chrominance signal, the U and V modulators are balanced ...
Page 10
... Figure and B inputs should remain constant dur- AVDD1 ing this interval. Sleep-Mode Load Checking When CE is high and an output driver is not active (i.e., sleep mode), the AD723 needs to check for the addition of a new CV load to the output. Rather than power up the output stage, a REMOTE 75 ...
Page 11
... Suitable delay should be included after turning the AD723 on before deciding to turn it off again because no load is detected. DC-Coupled Outputs The video outputs of the AD723 (Y, C and CV) are all dc- 2.3 s coupled. The advantages of this are two-fold. First, the need for 18 s large ac-coupling capacitors (220 µ ...
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... AD723 HSYNC/VSYNC (USER INPUTS) RIN/GIN BIN (USER INPUTS) MODULATOR RESTORE INPUT CLAMPS BURST FLAG/ DELAY LINE RESET Y C Symbol Name Description t Sync Width Input valid sync width for burst SW insertion (user-controlled). t Sync to Blanking Minimum sync to color delay SB End (user-controlled). t Sync to Modulator Delay to modulator clamp start ...
Page 13
... The logic inputs have been designed for VIL < 1.0 V and VIH > 2.0 V for the entire temperature and supply range of operation. This allows the AD723 to directly interface to TTL CMOS-compatible outputs, as well CMOS outputs where VOL is less than 1.0 V for 5 V operation. ...
Page 14
... AD723 Basic Connections Some simple applications will not require use of all of the fea- tures of the AD723. In such a case, some of the pins must be connected to appropriate levels such that the rest of the device can operate. Figure schematic of a very basic connection of the AD723. ...
Page 15
... The basic oscillator described above is buffered by U1B to drive the AD723 4FSC pin and other devices in the system. For a system that requires both an NTSC and PAL oscillator, the circuit can be duplicated by using a different pair of inverters from the same package ...
Page 16
... Such a signal is referred to as S-video or Y/C-video. Since the luminance and chromi- nance are already separated, the monitor does not have to perform this function. The S-video outputs of the AD723 can be used to create higher quality pictures when an S-video input is available on the monitor. ...
Page 17
... Synchronous vs. Asynchronous Operation The source of RGB video and synchronization used as an input to the AD723 in some systems is derived from the same clock signal as used for the AD723 subcarrier input (4FSC). These systems are said to be operating synchronously. In systems where two different clock sources are used for these signals, the operation is called asynchronous ...
Page 18
... AD723, 3.58 MHz for NTSC or 4.43 MHz for PAL. The circuit is shown in Figure 11. The 1.4 kΩ series resistor in the composite video luma path on the AD723 works against the impedance of the off-chip series LC to form a notch filter. The frequency of the filter is given by: ...
Page 19
... This signal should occur at the output of an on-chip XNOR gate on the AD723 whose two inputs are HSYNC (Pin 15) and VSYNC (Pin 16). There are several options for meeting these conditions. The first is to have separate signals for HSYNC and VSYNC. ...
Page 20
... AD723 PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE OUTLINE DIMENSIONS Dimensions shown in inches and (mm). (mm) are the controlling dimension. 28-Lead TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25 0.0433 (1.10) MAX 8 0 0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) BSC 0.0075 (0.19) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) ...