AD7273BRMZ-REEL Analog Devices Inc, AD7273BRMZ-REEL Datasheet - Page 8

• Manufacturer Part Number: AD7273BRMZ-REEL
• Description: IC,A/D CONVERTER,SINGLE,10-BIT,TSSOP,8PIN
• Manufacturer: Analog Devices Inc

Specifications of AD7273BRMZ-REEL

• Number Of Bits: 10
• Sampling Rate (per Second): 3M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 18mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7273/AD7274
TIMING EXAMPLES
For the AD7274, if CS is brought high during the 14
rising edge after the two leading zeros and 12 bits of the
conversion are provided, the part can achieve the fastest
throughput rate, 3 MSPS. If CS is brought high during the 16
SCLK rising edge after the two leading zeros, 12 bits of the
conversion, and two trailing zeros are provided, a throughput
rate of 2.97 MSPS is achievable. This is illustrated in the
following two timing examples.
Timing Example 1
In Figure 6, using a 14 SCLK cycle, f
the throughput is 3 MSPS. This produces a cycle time of
t
t
Figure 6 also shows that t
where t
satisfying the minimum requirement of 4 ns.
2
ACQ
+ 12.5(1/f
= 67 ns. This satisfies the requirement of 60 ns for t
9
= 4.2 ns max. This allows a value of 52.8 ns for t
SCLK
SDATA
SCLK
) + t
SCLK
CS
CS
ACQ
THREE-
STATE TWO LEADING
SDATA
SCLK
= 333 ns, where t
CS
ACQ
t
t
2
2
THREE-
STATE
Z
comprises 0.5(1/f
1
1
ZEROS
t
3
ZERO
t
2
TWO LEADING
Z
2
1
SCLK
2
t
ZEROS
3
ZERO
DB11
= 48 MHz, and
2
t
= 6 ns min and
CONVERT
3
3
2
DB10
12.5(1/f
DB11
SCLK
Figure 5. AD7274 Serial Interface Timing 16 SCLK Cycle
Figure 6.AD7274 Serial Interface Timing 14 SCLK Cycle
t
CONVERT
) + t
t
Figure 7. Serial Interface Timing 16 SCLK Cycle
CONVERT
4
SCLK
4
3
th
DB10
DB9
SCLK
9
t
t
)
6
4
+ t
QUIET
5
ACQ
QUIET
5
4
DB9
.
th
,
Rev. 0 | Page 8 of 28
t
t
6
4
,
12
1/THROUGHPUT
1/THROUGHPUT
5
1/THROUGHPUT
DB1
t
7
13
13
B
DB1
B
DB0
Timing Example 2
The example in Figure 7 uses a 16 SCLK cycle, f
and the throughput is 2.97 MSPS. This produces a cycle time
of t
t
t
requirement of 4 ns for t
t
ACQ
8
7
+ t
2
14
= 70 ns. Figure 7 shows that t
13
+ 12.5(1/f
t
QUIET
14
5
t
5
ZERO
B
DB0
TWO TRAILING
, where t
ZEROS
15
14
15
t
8
ZERO
t
SCLK
8
t
9
t
ACQUISITION
THREE-STATE
8
16
) + t
= 14 ns max. This satisfies the minimum
16
t
QUIET
ACQ
THREE-STATE
t
QUIET.
1
= 336 ns, where t
t
t
QUIET
QUIET
t
ACQ
t
1
1
comprises 2.5(1/f
2
= 6 ns min and
SCLK
= 48 MHz,
SCLK
) +