AD7352BRUZ-500RL7 Analog Devices Inc, AD7352BRUZ-500RL7 Datasheet - Page 15

• Manufacturer Part Number: AD7352BRUZ-500RL7
• Description: 12-Bit Dual Diff Simult 3 MSPS ADC I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7352BRUZ-500RL7

• Design Resources: DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7352 (CN0040)
• Number Of Bits: 12
• Sampling Rate (per Second): 3M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 45mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MODES OF OPERATION
The mode of operation of the AD7352 is selected by controlling
the logic state of the CS signal during a conversion. There are
three possible modes of operation: normal mode, partial power-
down mode, and full power-down mode. After a conversion is
initiated, the point at which CS is pulled high determines which
power-down mode, if any, the device enters. Similarly, if already
in power-down mode, CS can control whether the device returns
to normal operation or remains in power-down mode.
These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for the
differing application requirements.
NORMAL MODE
Normal mode is intended for applications needing the fastest
throughput rates because the user does not have to worry about
any power-up times because the AD7352 remains fully powered
at all times. Figure 24 shows the general diagram of the
operation of the AD7352 in normal mode.
The conversion is initiated on the falling edge of CS , as described
in the
fully powered up at all times,
10 SCLK falling edges have elapsed after the falling edge of CS .
If CS is brought high any time after the 10
but before the 14
up; however, the conversion is terminated and SDATA and
SDATA
and access the conversion result for the AD7352, 14 serial clock
cycles are required. The SDATA lines do not return to three-
state after 14 SCLK cycles have elapsed but instead do so when
CS is brought high again. If CS is left low for another two SCLK
cycles, two trailing zeros are clocked out after the data. If CS is
left low for a further 14 SCLK cycles, the result for the other
ADC on board is also accessed on the same SDATA line (see
Figure 31
Once 32 SCLK cycles have elapsed, the SDATA line returns to
three-state on the 32
prior to this, the SDATA line returns to three-state at that point.
Thus, CS may idle low after 32 SCLK cycles until it is brought
high again sometime prior to the next conversion. The bus still
returns to three-state upon completion of the dual result read.
SDATA
SDATA
SCLK
CS
A
B
Serial Interface
B
go back into three-state. To complete the conversion
and the
1
th
Figure 24. Normal Mode Operation
Serial Interface
LEADING ZEROS + CONVERSION RESULT
SCLK falling edge, the part remains powered
nd
section. To ensure that the part remains
SCLK falling edge. If CS is brought high
CS must remain low until at least
section).
10
th
SCLK falling edge,
14
A
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When a data transfer is complete and SDATA
have returned to three-state, another conversion can be initiated
after the quiet time, t
(assuming the required acquisition time has been allowed).
PARTIAL POWER-DOWN MODE
Partial power-down mode is intended for use in applications in
which slower throughput rates are required. Either the ADC
is powered down between each conversion or a series of conver-
sions can be performed at a high throughput rate, and the ADC
is then powered between these bursts of several conversions. It
is recommended that the AD7352 not remain in partial power-
down mode for longer than 100 μs. When the AD7352 is in
partial power-down, all analog circuitry is powered down
except for the on-chip reference and reference buffers.
To enter partial power-down mode, the conversion process
must be interrupted by bringing CS high any time after the
second falling edge of SCLK and before the 10
SCLK, as shown in
in this window of SCLKs, the part enters partial power-down,
the conversion that was initiated by the falling edge of CS is
terminated, and SDATA
If CS is brought high before the second SCLK falling edge, the
part remains in normal mode and does not power down. This
avoids accidental power-down due to glitches on the CS line.
To exit this mode of operation and power up the AD7352 again,
perform a dummy conversion. The device begins to power up
on the falling edge of CS and continues to power up as long as
CS is held low until after the falling edge of the 10
device is fully powered up after approximately 333 ns have
elapsed (or one full conversion), and valid data results from
the next conversion, as shown in
high before the second falling edge of SCLK, the AD7352 again
goes into partial power-down. This avoids accidental power-up
due to glitches on the CS line. Although the device may begin to
power up on the falling edge of CS , it powers down again on the
rising edge of CS . If the AD7352 is already in partial power-down
mode and CS is brought high between the second and 10
falling edges of SCLK, the device enters full power-down mode.
SDATA
SDATA
SCLK
CS
A
B
Figure 25. Entering Partial Power-Down Mode
1
Figure 25
2
QUIET
A
, has elapsed by bringing CS low again
and SDATA
. When
Figure 26
CS has been brought high
B
go back into three-state.
10
THREE-STATE
. If
A
CS is brought
th
and SDATA
falling edge of
th
1
SCLK. The
AD7352
4
th
B