AD7394ARZ Analog Devices Inc, AD7394ARZ Datasheet - Page 8

• Manufacturer Part Number: AD7394ARZ
• Description: X2, 12-Bit, +3V UPwr DAC
• Manufacturer: Analog Devices Inc

Specifications of AD7394ARZ

• Settling Time: 60µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Number Of Channels: 2
• Resolution: 12b
• Conversion Rate: 17KSPS
• Interface Type: Serial (3-Wire)
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: R-2R
• Power Supply Requirement: Single
• Output Type: Voltage
• Integral Nonlinearity Error: ±2LSB
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7394
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
AGND
V
V
DGND
CS
CLK
SDI
LDA
RS
LDB
MSB
SHDN
V
V
OUTA
REF
DD
OUTB
Description
Analog Ground.
DAC A Voltage Output.
DAC Reference Voltage Input Terminal. Establishes DAC full-scale output voltage. Pin can be tied to V
Digital Ground. Should be tied to analog GND.
Chip Select, Active Low Input. Disables shift register loading when high. Does not affect LDA or LDB operation.
Clock Input. Positive edge clocks data into shift register, MSB data bit first.
Serial Data Input. Input data loads directly into the shift register.
Load DAC Register Strobe. Level sensitive active low. Transfers shift register data to DAC A register. Asynchronous
active low input. See Table 2 for operation.
Resets DAC register to zero condition or half-scale, depending on MSB pin logic level. Asynchronous active low input.
Load DAC Register Strobe. Level-sensitive active low. Transfers shift register data to DAC B register. Asynchronous
active low input. See Table 2 for operation.
Digital Input. Logic High presets DAC registers to half-scale 800
logic low clears all DAC registers to zero (000
Active Low Shutdown Control Input. Does not affect register contents as long as power is present on V
can be loaded into the shift register and DAC register during shutdown. When device is powered up the most
recent data loaded into the DAC register controls the DAC output.
Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V
DAC B Voltage Output.
AGND
V
DGND
V
OUTA
CLK
REF
SDI
CS
Figure 5. Pin Configuration
1
2
3
4
5
6
7
Rev. A | Page 8 of 16
(Not to Scale)
AD7394
TOP VIEW
H
) when the RS pin is strobed.
14
13
12
11
10
9
8
V
V
SHDN
MSB
LDB
RS
LDA
OUTB
DD
H
(sets MSB bit to one) when the RS pin is strobed;
DD
DD
pin.
. New data