AD7400AYRWZ-RL Analog Devices Inc, AD7400AYRWZ-RL Datasheet - Page 15

• Manufacturer Part Number: AD7400AYRWZ-RL
• Description: Isolated Sigma-Delta Modulator ADC I.C.
• Manufacturer: Analog Devices Inc
• Type: Modulatorr

Specifications of AD7400AYRWZ-RL

• Resolution (bits): 14 b
• Data Interface: Serial
• Voltage Supply Source: Single Supply
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sampling Rate (per Second): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DIGITAL FILTER
The overall system resolution and throughput rate is deter-
mined by the filter selected and the decimation rate used. The
higher the decimation rate, the greater the system accuracy, as
illustrated in Figure 25. However, there is a tradeoff between
accuracy and throughput rate and, therefore, higher decimal-
tion rates result in lower throughput solutions.
A Sinc
filter can be implemented on an FPGA or a DSP.
where DR is the decimation rate.
The following Verilog code provides an example of a Sinc
implementation on a Xilinx® Spartan-II 2.5 V FPGA. This code
can possibly be compiled for another FPGA, such as an Altera®
device. Note that the data is read on the negative clock edge in
this case, although it can be read on the positive edge, if preferred.
Figure 25 shows the effect of using different decimation rates
with various filter types.
/*`Data is read on negative clk edge*/
module DEC256SINC24B(mdata1, mclk1, reset,
DATA);
input
input
input
filtered*/
output [15:0] DATA;
integer location;
integer info_file;
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
3
90
80
70
60
50
40
30
20
10
Figure 25. SNR vs. Decimation Rate for Different Filter Types
H
filter is recommended for use with the AD7400A. This
0
(
mclk1;
reset;
mdata1;
1
z
)


 



1
1


Z
Z
DR

1


10

 

3
DECIMATION RATE
/*used to clk filter*/
/*used to reset filter*/
/*ip data to be
ip_data1;
acc1;
acc2;
acc3;
acc3_d1;
acc3_d2;
diff1;
/*filtered op*/
100
SINC
SINC
SINC
3
2
1
3
1k
filter
Rev. B | Page 15 of 20
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [15:0]
reg [7:0]
reg word_clk;
reg init;
/*Perform the Sinc ACTION*/
always @ (mdata1)
if(mdata1==0)
to a -1 for 2's comp */
else
/*ACCUMULATOR (INTEGRATOR)
Perform the accumulation (IIR) at the speed
of the modulator.
Z = one sample delay
MCLKOUT = modulators conversion bit rate
*/
always @ (negedge mclk1 or posedge reset)
if (reset)
else
/*DECIMATION STAGE (MCLKOUT/ WORD_CLK)
*/
always @ (posedge mclk1 or posedge reset)
if (reset)
else
always @ (word_count)
MCLKOUT
IP_DATA1
ip_data1 <= 0;
ip_data1 <= 1;
begin
acc1 <= 0;
acc2 <= 0;
acc3 <= 0;
end
begin
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
/*initialize acc registers on reset*/
/*perform accumulation process*/
word_count <= 0;
word_count <= word_count + 1;
word_clk <= word_count[7];
+
Z
Figure 26. Accumulator
ACC1+
+
diff2;
diff3;
diff1_d;
diff2_d;
DATA;
word_count;
Z
/* change from a 0
ACC2+
+
Z
AD7400A
ACC3+