AD7401AYRWZ-RL Analog Devices Inc, AD7401AYRWZ-RL Datasheet - Page 16

• Manufacturer Part Number: AD7401AYRWZ-RL
• Description: Isolated 16-Bit Sigma -Delta Modula I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7401AYRWZ-RL

• Number Of Bits: 16
• Sampling Rate (per Second): 20M
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 93.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7401EBZ - BOARD EVALUATION FOR AD7401
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7401A
DIGITAL FILTER
The overall system resolution and throughput rate is determined
by the filter selected and the decimation rate used. The higher
the decimation rate, the greater the system accuracy, as illus-
trated in Figure 26. However, there is a tradeoff between accuracy
and throughput rate and, therefore, higher decimation rates
result in lower throughput solutions. Note that for a given
bandwidth requirement, a higher MCLKIN frequency can allow
for higher decimation rates to be used, resulting in higher SNR
performance.
A sinc3 filter is recommended for use with the AD7401A. This
filter can be implemented on an FPGA or a DSP.
where DR is the decimation rate.
The following Verilog code provides an example of a sinc3 filter
implementation on a Xilinx® Spartan-II 2.5 V FPGA. This code
can possibly be compiled for another FPGA, such as an Altera®
device. Note that the data is read on the negative clock edge in
this case, although it can be read on the positive edge, if
preferred.
H
90
80
70
60
50
40
30
20
10
Figure 26. SNR vs. Decimation Rate for Different Filter Types
(
0
z
1
)
=
⎛
⎜ ⎜
⎝
(
(
1
1
−
−
Z
Z
DR
−
1
)
)
⎞
⎟ ⎟
⎠
3
10
DECIMATION RATE
100
SINC3
SINC2
SINC1
1k
Rev. B | Page 16 of 20
/*`Data is read on negative clk edge*/
module DEC256SINC24B(mdata1, mclk1, reset,
DATA);
input
input
input
filtered*/
output [15:0] DATA;
integer location;
integer info_file;
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [15:0]
reg [7:0]
reg word_clk;
reg init;
/*Perform the Sinc ACTION*/
always @ (mdata1)
if(mdata1==0)
to a -1 for 2's comp */
else
/*ACCUMULATOR (INTEGRATOR)
Perform the accumulation (IIR) at the speed
of the modulator.
IP_DATA1
MCLKIN
ip_data1 <= 0;
ip_data1 <= 1;
mclk1;
reset;
mdata1;
+
Z
Figure 27. Accumulator
ACC1+
+
/*used to clk filter*/
/*used to reset filter*/
/*ip data to be
ip_data1;
acc1;
acc2;
acc3;
acc3_d1;
acc3_d2;
diff1;
diff2;
diff3;
diff1_d;
diff2_d;
DATA;
word_count;
Z
/*filtered op*/
/* change from a 0
ACC2+
+
Z
ACC3+