AD7612BSTZ-RL Analog Devices Inc, AD7612BSTZ-RL Datasheet - Page 6
![IC,A/D CONVERTER,SINGLE,16-BIT,CMOS,QFP,48PIN](/photos/6/59/65923/505-48-lqfp_sml.jpg)
AD7612BSTZ-RL
Manufacturer Part Number
AD7612BSTZ-RL
Description
IC,A/D CONVERTER,SINGLE,16-BIT,CMOS,QFP,48PIN
Manufacturer
Analog Devices Inc
Series
PulSAR®r
Datasheet
1.AD7612BSTZ.pdf
(32 pages)
Specifications of AD7612BSTZ-RL
Number Of Bits
16
Sampling Rate (per Second)
750k
Data Interface
Serial, Parallel
Number Of Converters
1
Power Dissipation (max)
230mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-AD7612CB - BOARD EVALUATION AD7612EVAL-AD7612CBZ - BOARD EVALUATION FOR AD7612
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD7612BSTZ-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
AD7612
Parameter
SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES
Figure 43, and Figure 45)
1
2
3
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
DIVSCLK[0]
SYNC to SDCLK First Edge Delay Minimum
Internal SDCLK Period Minimum
Internal SDCLK Period Maximum
Internal SDCLK High Minimum
Internal SDCLK Low Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SDCLK Last Edge to SYNC Delay Minimum
BUSY High Width Maximum
In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.
In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load C
In serial master read during convert mode. See Table 4 for serial master read after convert mode.
External SDCLK, SCCLK Setup Time
External SDCLK Active Edge to SDOUT Delay
SDIN/SCIN Setup Time
SDIN/SCIN Hold Time
External SDCLK/SCCLK Period
External SDCLK/SCCLK High
External SDCLK/SCCLK Low
Warp Mode
Normal Mode
Impulse Mode
TO OUTPUT
NOTES
1. IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT ARE DEFINED WITH A MAXIMUM LOAD
C
L
Figure 2. Load Circuit for Digital Interface Timing,
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
SDOUT, SYNC, and SCLK Outputs, C
PIN
60pF
C
L
1.6mA
500µA
I
I
OL
OH
1.4V
L
= 10 pF
2
(See Figure 42,
Rev. 0 | Page 6 of 32
Symbol
t
t
t
t
t
t
t
t
t
18
19
19
20
21
22
23
24
28
Symbol
t
t
t
t
t
t
t
31
32
33
34
35
36
37
0
0
3
30
45
15
10
4
5
5
1.65
1.9
2.15
t
DELAY
0.8V
Min
5
2
5
5
25
10
10
L
of 10 pF; otherwise, the load is 60 pF maximum.
Figure 3. Voltage Reference Levels for Timing
0
1
20
60
90
30
25
20
8
7
2.35
2.6
2.85
2V
0.8V
Typ
1
0
20
120
180
60
55
20
35
35
3.75
4.00
4.25
2V
Max
18
1
1
20
240
360
120
115
20
90
90
6.53
6.78
7.03
t
2V
0.8V
DELAY
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
Unit
ns
ns
ns
ns
ns
ns
ns