AD7656BSTZ-1 Analog Devices Inc, AD7656BSTZ-1 Datasheet - Page 27

• Manufacturer Part Number: AD7656BSTZ-1
• Description: 6-CHANNEL 16-BIT SE BIPOLAR I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7656BSTZ-1

• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: Serial, Parallel
• Number Of Converters: 6
• Power Dissipation (max): 143mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7656-1EDZ - BOARD EVAL CONTROL AD7656-1EVAL-AD7656-1CBZ - BOARD EVAL FOR AD7656-1EVAL-AD7656CBZ - BOARD EVAL FOR AD7656
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Daisy-Chain Mode (DCEN = 1, SER/ PAR SEL = 1)
When reading conversion data back from the AD7656-1/AD7657-1/
AD7658-1 using three/two/one DOUT pins, it is possible to
configure the parts to operate in daisy-chain mode by using the
DCEN pin. This daisy-chain feature allows multiple AD7656-1/
AD7657-1/AD7658-1 devices to be cascaded together and is
useful for reducing the component count and wiring connections.
An example connection of two devices is shown in Figure 34.
This configuration shows two DOUT lines being used for each
device. Simultaneous sampling of the 12 analog inputs is possible
by using a common CONVST signal. The DB5, DB4, and DB3
data pins are used as the DCIN[A:C] data input pins for the
daisy-chain mode.
The rising edge of CONVST is used to initiate a conversion on
the AD7656-1/AD7657-1/AD7658-1. After the BUSY signal has
gone low to indicate that the conversion is complete, the user can
begin to read the data from the two devices. Figure 35 shows the
serial timing diagram when operating two AD7656-1/AD7657-1/
AD7658-1 devices in daisy-chain mode.
The CS falling edge is used to frame the serial transfer from the
AD7656-1/AD7657-1/AD7658-1 devices, to take the bus out of
three-state, and to clock out the MSB of the first conversion
result. In the example shown in
are simultaneously sampled. Two DOUT lines are used to read
the conversion results in this example.
transfer. During the first 48 SCLKs, the conversion data is
transferred from Device 2 to Device 1. DOUT A on Device 2
transfers conversion data from V1, V2, and V5 into DCIN A in
Device 1; DOUT B on Device 2 transfers conversion results from
V3, V4, and V6 to DCIN B in Device 1. During the first 48 SCLKs,
Device 1 transfers data into the digital host. DOUT A on Device 1
transfers conversion data from V1, V2, and V5; DOUT B on
Device 1 transfers conversion data from V3, V4, and V6. During
the last 48 SCLKs, Device 2 clocks out 0s, and Device 1 shifts the
data clocked in from Device 2 during the first 48 SCLKs into
the digital host. This example can also be implemented using
six 16-SCLK individually framed transfers if DCEN remains
high during the transfers.
Figure 35
CS frames a 96 SCLK
, all 12 ADC channels
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Figure 36 shows the timing if two AD7656-1/AD7657-1/AD7658-1
devices are configured in daisy-chain mode and are operating
with three DOUT lines. Assuming that a simultaneous sampling
of all 12 inputs occurs, the CS frames a 64 SCLK transfer during
the read operation. During the first 32 SCLKs of this transfer,
the conversion results from Device 1 are clocked into the digital
host and the conversion results from Device 2 are clocked into
Device 1. During the last 32 SCLKs of the transfer, the
conversion results from Device 2 are clocked out of Device 1
and into the digital host, and Device 2 clocks out 0s.
Standby/Partial Power-Down Modes of Operation
(SER/ PAR SEL = 0 or 1)
Each ADC pair can be individually placed into partial power-
down mode by bringing the CONVST signal low before the
falling edge of BUSY. To power the ADC pair back up, the
CONVST signal should be brought high to tell the ADC pair to
power up and place the track-and-hold amplifier into track
mode. After the power-up time from partial power-down has
elapsed, the CONVST signal should receive a rising edge to
initiate a valid conversion. In partial power-down mode, the
reference buffers remain powered up. When an ADC pair is in
partial power-down mode, conversions can still occur on the
other ADCs.
The AD7656-1/AD7657-1/AD7658-1 have a standby mode
whereby the devices can be placed into a low power consumption
mode (25 μW maximum). The AD7656-1/AD7657-1/AD7658-1
are placed into standby mode by bringing the logic input STBY
low and can be powered up again for normal operation by bringing
STBY logic high. The output data buffers are still operational
when the AD7656-1/AD7657-1/AD7658-1 are in standby
mode, meaning the user can continue to access the conversion
results of the parts. This standby feature can be used to reduce
the average power consumed by the AD7656-1/AD7657-1/
AD7658-1 when operating at lower throughput rates. The parts
can be placed into standby at the end of each conversion when
BUSY goes low and are taken out of standby mode prior to the
next conversion. The time for the AD7656-1/AD7657-1/
AD7658-1 to come out of standby is called the wake-up time.
The wake-up time limits the maximum throughput rate at which
the AD7656-1/AD7657-1/AD7658-1 can operate when powering
down between conversions. See the
AD7656-1/AD7657-1/AD7658-1
Specifications
section.