AD8250ARMZ-RL Analog Devices Inc, AD8250ARMZ-RL Datasheet - Page 15

• Manufacturer Part Number: AD8250ARMZ-RL
• Description: IC,Instrumentation Amplifier,SINGLE,CMOS,TSSOP,10PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: iCMOS®r

Specifications of AD8250ARMZ-RL

• Amplifier Type: Instrumentation
• Number Of Circuits: 1
• Output Type: Push-Pull
• Slew Rate: 25 V/µs
• -3db Bandwidth: 10MHz
• Current - Input Bias: 5nA
• Voltage - Input Offset: 70µV
• Current - Supply: 4.1mA
• Current - Output / Channel: 37mA
• Voltage - Supply, Single/dual (±): 10 V ~ 30 V, ±5 V ~ 15 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD8250-EVALZ - BOARD EVALUATION AD8250
• Gain Bandwidth Product: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
The AD8250 is a monolithic instrumentation amplifier based
on the classic, 3-op-amp topology as shown in Figure 47. It is
fabricated on the Analog Devices, Inc., proprietary iCMOS®
process that provides precision, linear performance, and a
robust digital interface. A parallel interface allows users to
digitally program gains of 1, 2, 5, and 10. Gain control is achieved
by switching resistors in an internal, precision resistor array (as
shown in Figure 47). Although the AD8250 has a voltage feedback
topology, the gain bandwidth product increases for gains of 1, 2,
and 5 because each gain has its own frequency compensation.
This results in maximum bandwidth at higher gains.
All internal amplifiers employ distortion cancellation circuitry
and achieve high linearity and ultralow THD. Laser trimmed
resistors allow for a maximum gain error of less than 0.03%
for G = 1 and minimum CMRR of 98 dB for G = 10. A pinout
optimized for high CMRR over frequency enables the AD8250
to offer a guaranteed minimum CMRR over frequency of 80 dB
at 50 kHz (G = 1). The balanced input reduces the parasitics
that, in the past, adversely affected CMRR performance.
GAIN SELECTION
Logic low and logic high voltage limits are listed in the
Specifications section. Typically, logic low is 0 V and logic high
is 5 V; both voltages are measured with respect to DGND. See
Table 2 for the permissible voltage range of DGND. The gain of
the AD8250 can be set using two methods.
+IN
–IN
2.2kΩ
2.2kΩ
+V
+V
–V
–V
S
S
S
S
A1
A2
WR
DIGITAL
GAIN
CONTROL
A0
Figure 47. Simplified Schematic
+V
+V
–V
–V
S
S
S
S
Rev. B | Page 15 of 24
2.2kΩ
2.2kΩ
+V
–V
+V
–V
10kΩ
10kΩ
S
S
S
S
Transparent Gain Mode
The easiest way to set the gain is to program it directly via a
logic high or logic low voltage applied to A0 and A1. Figure 48
shows an example of this gain setting method, referred to through-
out the data sheet as transparent gain mode. Tie WR to the negative
supply to engage transparent gain mode. In this mode, any change
in voltage applied to A0 and A1 from logic low to logic high, or
vice versa, immediately results in a gain change.
truth table for transparent gain mode, and
AD8250 configured in transparent gain mode.
A1
DGND
Figure 48. Transparent Gain Mode, A0 and A1 = High, G = 10
A3
NOTE:
1. IN TRANSPARENT GAIN MODE, WR IS TIED TO −V
10kΩ
10kΩ
THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE
THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE
SET TO LOGIC HIGH, RESULTING IN A GAIN OF 10.
–IN
+IN
10μF
10μF
+V
–V
+V
–V
0.1µF
0.1µF
S
S
S
S
OUT
REF
+15V
–15V
AD8250
DGND
WR
A1
A0
REF
DGND
Figure 48
–15V
+5V
+5V
G = 10
S
Table 5
.
shows the
AD8250
is the