AD8250ARMZ-RL Analog Devices Inc, AD8250ARMZ-RL Datasheet - Page 16

• Manufacturer Part Number: AD8250ARMZ-RL
• Description: IC,Instrumentation Amplifier,SINGLE,CMOS,TSSOP,10PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: iCMOS®r

Specifications of AD8250ARMZ-RL

• Amplifier Type: Instrumentation
• Number Of Circuits: 1
• Output Type: Push-Pull
• Slew Rate: 25 V/µs
• -3db Bandwidth: 10MHz
• Current - Input Bias: 5nA
• Voltage - Input Offset: 70µV
• Current - Supply: 4.1mA
• Current - Output / Channel: 37mA
• Voltage - Supply, Single/dual (±): 10 V ~ 30 V, ±5 V ~ 15 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD8250-EVALZ - BOARD EVALUATION AD8250
• Gain Bandwidth Product: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD8250
Table 5. Truth Table Logic Levels for Transparent Gain Mode
WR
−V
−V
−V
−V
Latched Gain Mode
Some applications have multiple programmable devices such as
multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a
data bus. The gain of the AD8250 can be set using WR as a latch,
allowing other devices to share A0 and A1.
schematic using this method, known as latched gain mode. The
AD8250 is in this mode when
low, typically 5 V and 0 V, respectively. The voltages on A0
and A1 are read on the downward edge of the WR signal as it
transitions from logic high to logic low. This latches in the logic
levels on A0 and A1, resulting in a gain change. See the truth
table in
S
S
S
S
NOTE:
1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS
FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0
AND A1 ARE READ AND LATCHED IN, RESULTING IN A
GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 10.
Table 6
–IN
+IN
10μF
10μF
for more information on these gain changes.
Figure 49. Latched Gain Mode, G = 10
A1
Low
Low
High
High
0.1µF
0.1µF
+15V
–15V
+
–
AD8250
DGND
WR
WR is held at logic high or logic
A1
A0
Low
High
Low
High
A0
REF
G = PREVIOUS
STATE
DGND
WR
A1
A0
A0, A1
WR
Figure 49
Gain
1
2
5
10
G = 10
Figure 50. Timing Diagram for Latched Gain Mode
+5V
0V
+5V
0V
+5V
0V
shows a
t
WR-HIGH
Rev. B | Page 16 of 24
t
SU
t
HD
t
WR-LOW
Table 6. Truth Table Logic Levels for Latched Gain Mode
WR
High to low
High to low
High to low
High to low
Low to low
Low to high
High to high
1
On power-up, the AD8250 defaults to a gain of 1 when in latched
gain mode. In contrast, if the AD8250 is configured in transparent
gain mode, it starts at the gain indicated by the voltage levels on
A0 and A1 at power-up.
Timing for Latched Gain Mode
In latched gain mode, logic levels at A0 and A1 have to be held
for a minimum setup time, t
WR latches in the gain. Similarly, they must be held for a
minimum hold time of t
ensure that the gain is latched in correctly. After t
can change logic levels, but the gain does not change (until the
next downward edge of WR ). The minimum duration that WR
can be held high is t
WR can be held low is t
listed in
by the settling time of the amplifier. A timing diagram is shown
in
When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8250. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog portions
of the board. Pull-up or pull-down resistors should be used to
provide a well-defined voltage at the A0 and A1 pins.
X = don’t care.
Figure 50
Table 2.
.
The time required for a gain change is dominated
A1
Low
Low
High
High
X
X
X
WR
1
1
1
-HIGH
WR
HD
-LOW
after the downward edge of WR to
, and the minimum duration that
SU
A0
Low
High
Low
High
X
X
X
, before the downward edge of
. Digital timing specifications are
1
1
1
Gain
Change to 1
Change to 2
Change to 5
Change to 10
No change
No change
No change
HD
, A0 and A1