AD9216BCPZRL7-65 Analog Devices Inc, AD9216BCPZRL7-65 Datasheet - Page 9
![IC,A/D CONVERTER,DUAL,10-BIT,CMOS,LLCC,64PIN](/photos/6/50/65021/505-64-lfcsp_sml.jpg)
AD9216BCPZRL7-65
Manufacturer Part Number
AD9216BCPZRL7-65
Description
IC,A/D CONVERTER,DUAL,10-BIT,CMOS,LLCC,64PIN
Manufacturer
Analog Devices Inc
Datasheet
1.AD9216BCPZ-65.pdf
(40 pages)
Specifications of AD9216BCPZRL7-65
Number Of Bits
10
Sampling Rate (per Second)
65M
Data Interface
Parallel
Number Of Converters
2
Power Dissipation (max)
240mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
1, 4, 13, 16
2
3
5, 12, 17, 64
6
7
8
9
10
11
14
15
18
19
20
21
22
23 to 26, 39,
42 to 45, 58
27, 30 to 38
28, 40, 53
29, 41, 52
Mnemonic
AGND
VIN+_A
VIN−_A
AVDD
REFT_A
REFB_A
VREF
SENSE
REFB_B
REFT_B
VIN−_B
VIN+_B
CLK_B
DCS
DFS
PDWN_B
OEB_B
DNC
D0_B (LSB) to
D9_B (MSB)
DRGND
DRVDD
1
Description
Analog Ground.
Analog Input Pin (+) for Channel A.
Analog Input Pin (−) for Channel A.
Analog Power Supply.
Differential Reference (+) for Channel A.
Differential Reference (−) for Channel A.
Voltage Reference Input/Output.
Reference Mode Selection.
Differential Reference (−) for Channel B.
Differential Reference (+) for Channel B.
Analog Input Pin (−) for Channel B.
Analog Input Pin (+) for Channel B.
Clock Input Pin for Channel B.
Duty Cycle Stabilizer (DCS) Mode Pin (Active High).
Data Output Format Select Pin. Low for offset binary; high for twos complement.
Power-Down Function Selection for Channel B.
Output Enable for Channel B.
Do Not Connect Pins. Should be left floating.
Channel B Data Output Bits.
Digital Output Ground.
Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor.
Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF.
Logic 0 enables Data Bus B.
Logic 1 sets outputs to High-Z.
Logic 0 enables Channel B.
Logic 1 powers down Channel B. (Outputs static, not High-Z.)
REFB_A
REFB_B
DNC =
DO NOT CONNECT
REFT_A
REFT_B
VIN+_A
VIN–_A
VIN–_B
VIN+_B
SENSE
AGND
AGND
AGND
AGND
AVDD
AVDD
VREF
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Figure 3. Pin Configuration
Rev. A | Page 9 of 40
(Not to Scale)
AD9216
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D2_A
D1_A
D0_A (LSB)
DNC
DNC
DNC
DNC
DRVDD
DRGND
DNC
D9_B (MSB)
D8_B
D7_B
D6_B
D5_B
D4_B
AD9216