AD9228BCPZRL7-65 Analog Devices Inc, AD9228BCPZRL7-65 Datasheet
AD9228BCPZRL7-65
Specifications of AD9228BCPZRL7-65
Related parts for AD9228BCPZRL7-65
AD9228BCPZRL7-65 Summary of contents
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FEATURES 4 ADCs integrated into 1 package 119 mW ADC power per channel at 65 MSPS SNR = 70 dB (to Nyquist) ENOB = 11.3 bits SFDR = 82 dBc (to Nyquist) Excellent linearity DNL = ±0.3 LSB (typical) INL ...
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AD9228 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 AC Specifications .......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications ...
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REVISION HISTORY 4/10—Rev Rev. D Changes to Table 16 ........................................................................ 35 Updated Outline Dimensions ........................................................ 53 Changes to Ordering Guide ........................................................... 53 12/09—Rev Rev. C Updated Outline Dimensions ........................................................ 53 Changes to Ordering Guide ........................................................... 54 ...
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AD9228 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain ...
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AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR 2.4 MHz ...
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AD9228 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage ...
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SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4. 1 Temp , 2 Parameter 3 CLOCK Maximum Clock Rate Full Minimum ...
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AD9228 TIMING DIAGRAMS N – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – – 1 VIN ± ...
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N – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – FRAME t DATA LSB ...
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AD9228 ABSOLUTE MAXIMUM RATINGS Table 5. With Parameter Respect To ELECTRICAL AVDD AGND DRVDD DRGND AGND DRGND AVDD DRVDD Digital Outputs DRGND ( − x, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− AGND VIN + x, VIN − ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVDD AVDD VIN – D VIN + D AVDD AVDD CLK– CLK+ AVDD AVDD DRGND DRVDD NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND. Table 7. Pin Function Descriptions Pin No. Mnemonic ...
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AD9228 Pin No. Mnemonic 33 VIN + A 34 VIN − VIN − VIN + B 40 RBIAS 41 SENSE 42 VREF 43 REFB 44 REFT 47 VIN + C 48 VIN − C Description ADC ...
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EQUIVALENT CIRCUITS VIN ± x Figure 6. Equivalent Analog Input Circuit 10Ω CLK+ 10kΩ 10kΩ 10Ω CLK– Figure 7. Equivalent Clock Input Circuit 350Ω SDIO/ODM 30kΩ Figure 8. Equivalent SDIO/ODM Input Circuit 1.25V SCLK/DTP Rev Page 13 of ...
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AD9228 AVDD 70kΩ 1kΩ CSB Figure 12. Equivalent CSB Input Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit VREF Figure 14. Equivalent VREF Circuit Rev Page 6kΩ ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0 –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 15. Single-Tone 32k FFT with f = 2.4 MHz –20 –40 –60 –80 –100 –120 0 2 ...
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AD9228 0 –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 21. Single-Tone 32k FFT with f = 190 MHz –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure ...
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40MSPS SAMPLE 80 2V p-p, SFDR 70 60 80dB 50 REFERENCE –60 –50 –40 –30 ANALOG INPUT LEVEL (dBFS) Figure 27. SNR/SFDR vs. Analog Input Level, f ...
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AD9228 0 AIN1 AND AIN2 = –7dBFS –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 33. Two-Tone 32k FFT with MHz and f IN1 MSPS SAMPLE 0 AIN1 AND ...
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FREQUENCY (MHz) Figure 39. CMRR vs. Frequency MSPS SAMPLE 1.2 0.26 LSB rms 1.0 0.8 0.6 0.4 0 – – ...
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AD9228 THEORY OF OPERATION The AD9228 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors ...
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SFDR (dBc SNR (dB 0.2 0.4 0.6 0.8 1.0 1.2 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 44. SNR/SFDR vs. Common-Mode Voltage 2.4 MHz MSPS IN SAMPLE ...
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AD9228 For best dynamic performance, the source impedances driving VIN + x and VIN − x should be matched such that common- mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal ...
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CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9228 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK − pins via a transformer or capacitors. These pins ...
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AD9228 Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (f due only to aperture jitter (t ) can be calculated by J ...
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By asserting the PDWN pin high, the AD9228 is placed into power-down mode. In this state, the ADC typically dissipates 3 mW. During power-down, the LVDS output drivers are placed into a high impedance state. If any of the SPI ...
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AD9228 EYE: ALL BITS 500 0 –500 –1ns –0.5ns 0ns 100 50 0 –100ps 0ps Figure 61. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination ...
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Two output clocks are provided to assist in capturing data from the AD9228. The DCO is used to clock the output data and is equal to six times the sample clock (CLK) rate. Data is clocked out of the AD9228 ...
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AD9228 When the SPI is used, the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO+ and DCO− timing, as shown in ...
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SCLK/DTP Pin The SCLK/DTP pin is for use in applications that do not require SPI mode operation. This pin can enable a single digital test pattern if it and the CSB pin are held high during device power- up. When ...
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AD9228 Internal Reference Operation A comparator within the AD9228 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 64), setting VREF ...
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SERIAL PORT INTERFACE (SPI) The AD9228 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided in the ADC. This may provide the user with additional flexibility and customization, ...
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AD9228 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 68. SDIO Pin Loading ...
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MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map register table (Table 16) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the ...
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AD9228 Table 16. Memory Map Register Addr. (MSB) (Hex) Register Name Bit 7 Bit 6 Chip Configuration Registers 00 chip_port_config 0 LSB first off (default) 01 chip_id 02 chip_grade X Child ID [6:4] (identify device ...
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Addr. (MSB) (Hex) Register Name Bit 7 Bit 6 14 output_mode LVDS ANSI-644 (default LVDS low power (IEEE 1596.3 similar) 15 output_adjust output_phase user_patt1_lsb user_patt1_msb B15 ...
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AD9228 Power and Ground Recommendations When connecting power to the AD9228 recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be ...
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EVALUATION BOARD The AD9228 evaluation board provides all of the support cir- cuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially using a transformer (default AD8332 driver. The ADC ...
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AD9228 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9228 Rev. A evaluation board. • POWER: Connect the switching power supply that is provided with the ...
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ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION The following is a brief description of the alternative analog input drive configuration using the AD8332 dual VGA. If this drive option is in use, some components may need to be populated, in which case ...
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AD9228 VGA INPUT CONNECTION INH1 CHANNEL A R101 P101 DNP AIN R102 64.9Ω VGA INPUT CONNECTION CHANNEL B P103 AIN P106 DNP VGA INPUT CONNECTION INH3 AIN CHANNEL C R127 P105 DNP AIN R129 R128 0Ω 64.9Ω AVDD_DUT VGA INPUT ...
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AVDD_DUT V– DNP - 100kΩ R267 DNP - 100kΩ R266 VIN_B B – VIN 37 VIN_B B + VIN 38 AVDD_DUT AVDD 39 RBIAS 40 SENSE VSENSE_DUT 41 VREF VREF_DUT 42 REFB 43 REFT 44 AVDD AVDD_DUT ...
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AD9228 POPULATE L301-L308 WITH 0Ω RESISTORS OR DESIGN YOUR OWN FILTER. 10kΩ R313 10kΩ DNP C311 0.1µF C312 0.1µF R315 C315 10kΩ 10µF DNP: DO NOT POPULATE Figure 75. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface ...
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SDO_CHA 0Ω R427 SDI_CHA 0Ω R420 SCLK_CHA 0Ω R428 CSB1_CHA 0Ω R426 ±75mV = H = PIN ±50mV = LO = PIN PIN RCLAMP AVDD_5V FILTER. OWN YOUR DESIGN OR RESISTORS 0Ω WITH L401-L408 POPULATE CH_A CH_A AVDD_5V CH_B CH_B ...
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AD9228 Figure 77. Evaluation Board Schematic, Power Supply Inputs Rev Page 05727-019 GND GND 1 1 GND GND 1 1 ...
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Figure 78. Evaluation Board Layout, Primary Side Rev Page AD9228 ...
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AD9228 Figure 79. Evaluation Board Layout, Ground Plane Rev Page ...
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Figure 80. Evaluation Board Layout, Power Plane Rev Page AD9228 ...
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AD9228 Figure 81. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page ...
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Table 17. Evaluation Board Bill of Materials (BOM) Item Qty. Reference Designator 1 1 AD9228LFCSP_REVA 2 75 C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C203, C204, C205, C206, C210, C211, C212, C213, C216, C217, ...
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AD9228 Item Qty. Reference Designator 17 1 F501 18 1 FER501 19 12 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112 20 1 JP301 21 2 J205, J402 22 1 J201 to J204 23 1 J401 ...
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Item Qty. Reference Designator 35 15 R109, R111, R112, R123, R125, R126, R135, R138, R139, R148, R149, R150, R431, R432, R433 36 8 R108, R110, R121, R122, R134, R136, R146, R147 37 4 R161, R162, R163, R164 38 3 R202, ...
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AD9228 Item Qty. Reference Designator 57 2 U301, U401 58 1 U504 59 1 U502 60 1 U201 61 1 U203 62 1 U202 63 1 U403 64 1 U404 65 1 U402 1 This BOM is RoHS compliant. Device ...
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OUTLINE DIMENSIONS PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range 2 AD9228ABCPZ-40 −40°C to +85°C 2 AD9228ABCPZRL7-40 −40°C to +85°C 2 AD9228ABCPZ-65 −40°C to +85°C AD9228ABCPZRL7-65 2 −40°C to +85°C ...
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AD9228 NOTES Rev Page ...
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NOTES Rev Page AD9228 ...
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AD9228 NOTES ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05727-0-4/10(D) Rev Page ...